| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 04/17/2001 | US6218734 Copper adhered to a diffusion barrier surface |
| 04/17/2001 | US6218733 Semiconductor device having a titanium-aluminum compound |
| 04/17/2001 | US6218732 Copper bond pad process |
| 04/17/2001 | US6218727 Wafer frame |
| 04/17/2001 | US6218725 Bipolar transistors with isolation trenches to reduce collector resistance |
| 04/17/2001 | US6218724 Thin film transistor used in semiconductor memory for achieving reduction in power consumption |
| 04/17/2001 | US6218723 Integrated capacitor with high voltage linearity and low series resistance |
| 04/17/2001 | US6218720 Semiconductor topography employing a nitrogenated shallow trench isolation structure |
| 04/17/2001 | US6218716 Enhanced structure for salicide MOSFET |
| 04/17/2001 | US6218714 Insulated gate semiconductor device and method of manufacturing the same |
| 04/17/2001 | US6218713 Logical circuit, flip-flop circuit and storage circuit with multivalued logic |
| 04/17/2001 | US6218712 Semiconductor device and method of manufacturing same |
| 04/17/2001 | US6218711 Raised source/drain process by selective sige epitaxy |
| 04/17/2001 | US6218710 Method to ensure isolation between source-drain and gate electrode using self aligned silicidation |
| 04/17/2001 | US6218709 Semiconductor device and semiconductor circuit using the same |
| 04/17/2001 | US6218706 Integrated circuit with improved electrostatic discharge protection circuitry |
| 04/17/2001 | US6218705 Semiconductor device having protective element to conduct current to substrate |
| 04/17/2001 | US6218704 ESD protection structure and method |
| 04/17/2001 | US6218703 Semiconductor device with control electrodes formed from semiconductor material |
| 04/17/2001 | US6218702 Microcrystal silicon film and its manufacturing method, and photoelectric conversion device and its manufacturing method |
| 04/17/2001 | US6218701 Power MOS device with increased channel width and process for forming same |
| 04/17/2001 | US6218700 Remanent memory device |
| 04/17/2001 | US6218699 Semiconductor component with adjustable current amplification based on a tunnel-current-controlled avalanche breakdown |
| 04/17/2001 | US6218698 Apparatus and method for container floating gate cell |
| 04/17/2001 | US6218697 Contact in semiconductor memory device |
| 04/17/2001 | US6218696 Layout and wiring scheme for memory cells with vertical transistors |
| 04/17/2001 | US6218695 Area efficient column select circuitry for 2-bit non-volatile memory cells |
| 04/17/2001 | US6218694 Semiconductor memory device and method for manufacturing same |
| 04/17/2001 | US6218693 Dynamic random access memory (DRAM) cell having a buried horizontal trench capacitor by a novel fabrication method |
| 04/17/2001 | US6218690 Transistor having reverse self-aligned structure |
| 04/17/2001 | US6218689 Method for providing a dopant level for polysilicon for flash memory devices |
| 04/17/2001 | US6218685 Semiconductor device and method for fabricating the same |
| 04/17/2001 | US6218680 Semi-insulating silicon carbide without vanadium domination |
| 04/17/2001 | US6218678 Semiconductor device |
| 04/17/2001 | US6218674 Electron beam projection exposure apparatus |
| 04/17/2001 | US6218671 On-line dynamic corrections adjustment method |
| 04/17/2001 | US6218631 Structure for reducing cross-talk in VLSI circuits and method of making same using filled channels to minimize cross-talk |
| 04/17/2001 | US6218629 Module with metal-ion matrix induced dendrites for interconnection |
| 04/17/2001 | US6218628 Foil circuit boards and semifinished products and method for the manufacture thereof |
| 04/17/2001 | US6218320 Method for improving the uniformity of wafer-to-wafer film thickness |
| 04/17/2001 | US6218319 Method of forming an arsenic silicon glass film onto a silicon structure |
| 04/17/2001 | US6218318 Semiconductor device having a porous insulation film |
| 04/17/2001 | US6218317 Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration |
| 04/17/2001 | US6218316 Planarization of non-planar surfaces in device fabrication |
| 04/17/2001 | US6218315 HTO (high temperature oxide) deposition for capacitor dielectrics |
| 04/17/2001 | US6218314 Forming alluminum alloy layer over dielectric layer on semiconductor structure; forming silicon dioxide layer, silicon oxide/ silicon oxynitride transition layer and silicon oxynitride layer in chemical vapor deposition chamber |
| 04/17/2001 | US6218313 Process for producing semiconductor device, apparatus for optimizing film thickness, and process for optimizing film thickness |
| 04/17/2001 | US6218312 Plasma reactor with heated source of a polymer-hardening precursor material |
| 04/17/2001 | US6218311 Post-etch treatment of a semiconductor device |
| 04/17/2001 | US6218310 RTA methods for treating a deep-UV resist mask prior to gate formation etch to improve gate profile |
| 04/17/2001 | US6218309 Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features |
| 04/17/2001 | US6218308 Method of manufacturing a contact for a capacitor of high density DRAMs |
| 04/17/2001 | US6218307 Method of fabricating shallow trench isolation structure |
| 04/17/2001 | US6218306 Method of chemical mechanical polishing a metal layer |
| 04/17/2001 | US6218305 Polishing composite comprised of silica and silicon nitride using polishing slurry comprising aqueous medium, abrasive particles, surfactant, organic polymer viscosity modifier and compound which complexes with the silica and silicon nitride |
| 04/17/2001 | US6218304 Method of determining copper reduction endpoint in the fabrication of a semiconductor device |
| 04/17/2001 | US6218303 Via formation using oxide reduction of underlying copper |
| 04/17/2001 | US6218302 Method for forming a semiconductor device |
| 04/17/2001 | US6218301 Treating substrate with dielectric material thereon using gas mixture comprising silicon compound; forming tungsten films on substrate |
| 04/17/2001 | US6218300 Placing substrate in deposition chamber; providing deposition gas mix comprising sources of tantalum, titanium, and oxygen containing gas into chamber; decomposing source of tantalum and titanium; reacting to form dielectric layer film |
| 04/17/2001 | US6218299 Semiconductor device and method for producing the same |
| 04/17/2001 | US6218298 Heating silicon substrate while flowing mixture consisting of tungsten fluoride(wf.sub.6), hydrogen and silicon hydride(sih.sub.4) for forming over walls of trench a nucleation film and to fill trench |
| 04/17/2001 | US6218297 Patterning conductive metal layers and methods using same |
| 04/17/2001 | US6218296 Semiconductor device with pillar-shaped capacitor storage node and method of fabricating the same |
| 04/17/2001 | US6218295 Semiconductor structure with a titanium aluminum nitride layer and method for fabricating the same |
| 04/17/2001 | US6218294 Method of manufacturing interconnect |
| 04/17/2001 | US6218293 Using a diffusion furnace |
| 04/17/2001 | US6218292 Dual layer bottom anti-reflective coating |
| 04/17/2001 | US6218291 Method for forming contact plugs and simultaneously planarizing a substrate surface in integrated circuits |
| 04/17/2001 | US6218290 Copper dendrite prevention by chemical removal of dielectric |
| 04/17/2001 | US6218289 Method for contact anneal in a doped dielectric layer without dopant diffusion problem |
| 04/17/2001 | US6218288 Multiple step methods for forming conformal layers |
| 04/17/2001 | US6218287 Method of fabricating a semiconductor structure |
| 04/17/2001 | US6218286 Isolation dielectric deposition in multi-polysilicon chemical-mechanical polishing process |
| 04/17/2001 | US6218285 Dielectric and aluminum nitride layers |
| 04/17/2001 | US6218284 Method for forming an inter-metal dielectric layer |
| 04/17/2001 | US6218283 Method of fabricating a multi-layered wiring system of a semiconductor device |
| 04/17/2001 | US6218282 Method of forming low dielectric tungsten lined interconnection system |
| 04/17/2001 | US6218281 Semiconductor device with flip chip bonding pads and manufacture thereof |
| 04/17/2001 | US6218280 High pressure vapor deposition |
| 04/17/2001 | US6218279 Vertical fuse and method of fabrication |
| 04/17/2001 | US6218278 Method of forming a conducting structure |
| 04/17/2001 | US6218277 Method for filling a via opening or contact opening in an integrated circuit |
| 04/17/2001 | US6218276 Silicide encapsulation of polysilicon gate and interconnect |
| 04/17/2001 | US6218275 Process for forming self-aligned contact of semiconductor device |
| 04/17/2001 | US6218274 Semiconductor device and manufacturing method thereof |
| 04/17/2001 | US6218273 Methods of forming isolation trenches in integrated circuits using protruding insulating layers |
| 04/17/2001 | US6218272 Method for fabricating conductive pad |
| 04/17/2001 | US6218271 Method of forming a landing pad on the drain and source of a MOS transistor |
| 04/17/2001 | US6218270 Method of manufacturing semiconductor device having shallow junction |
| 04/17/2001 | US6218269 Process for producing III-V nitride pn junctions and p-i-n junctions |
| 04/17/2001 | US6218268 Two-step borophosphosilicate glass deposition process and related devices and apparatus |
| 04/17/2001 | US6218267 Shallow trench isolation method of a semiconductor wafer |
| 04/17/2001 | US6218266 Method of fabricating electronic devices of the type including smoothing process using polishing |
| 04/17/2001 | US6218265 Process for fabricating a semiconductor non-volatile memory device with shallow trench isolation (STI) |
| 04/17/2001 | US6218264 Method of producing a calibration standard for 2-D and 3-D profilometry in the sub-nanometer range |
| 04/17/2001 | US6218263 Method of forming an alignment key on a semiconductor wafer |
| 04/17/2001 | US6218262 Semiconductor device and method of manufacturing the same |
| 04/17/2001 | US6218261 Method of fabricating bottom electrode |
| 04/17/2001 | US6218260 Methods of forming integrated circuit capacitors having improved electrode and dielectric layer characteristics and capacitors formed thereby |