| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 04/10/2001 | US6214739 Forming semiconductors by etching metal layers, photoresists masking and dry etching |
| 04/10/2001 | US6214738 Aluminum workpiece treated with focused radiation beams and treatment with anodic oxidation |
| 04/10/2001 | US6214737 Simplified sidewall formation for sidewall patterning of sub 100 nm structures |
| 04/10/2001 | US6214736 Providing first and second species over silicon substrate, first species oxidizes silicon and diffuses through silicon dioxide, second species volatilizes silicon dioxide, removing silicon with equilibrium silicon dioxide layer |
| 04/10/2001 | US6214735 Method for planarizing a semiconductor substrate |
| 04/10/2001 | US6214734 Method of using films having optimized optical properties for chemical mechanical polishing endpoint detection |
| 04/10/2001 | US6214733 Process for lift off and handling of thin film materials |
| 04/10/2001 | US6214732 Chemical mechanical polishing endpoint detection by monitoring component activity in effluent slurry |
| 04/10/2001 | US6214731 Forming opening in dielectric layer, lining with barrier metal layer, treating exposed surface of lining with silane or dichlorosilane to form thin layer of silicon, depositing layer of copper or copper alloy, reacting to form copper silicide |
| 04/10/2001 | US6214730 Fluorine barrier layer between conductor and insulator for degradation prevention |
| 04/10/2001 | US6214728 Forming hole in insulation layer down to doped silicon substrate surface, forming metal diffusion barrier on walls and bottom of hole, filling with copper to predetermined depth, depositing encapsulating metal to fill hole, polishing |
| 04/10/2001 | US6214727 Conductive electrical contacts, capacitors, DRAMs, and integrated circuitry, and methods of forming conductive electrical contacts, capacitors, DRAMs, and integrated circuitry |
| 04/10/2001 | US6214726 Method of producing rough polysilicon by the use of pulsed plasma chemical vapor deposition and products produced by same |
| 04/10/2001 | US6214725 Etching first film of stacked film with first etching gas including chlorine, etching second film with compound gas containing chlorine atom mixed with additive gas to improve corrosion resistance of aluminum-copper alloy film |
| 04/10/2001 | US6214724 Forming gate insulating film on semiconductor substrate, forming conductive metal oxide film on gate insulating film to make stacked-layer film, forming gate electrode by etching stacked-layer film |
| 04/10/2001 | US6214723 Method of manufacturing a semiconductor device |
| 04/10/2001 | US6214722 Method for improving wafer topography to provide more accurate transfer of interconnect patterns |
| 04/10/2001 | US6214721 Method and structure for suppressing light reflections during photolithography exposure steps in processing integrated circuit structures |
| 04/10/2001 | US6214720 Plasma process enhancement through reduction of gaseous contaminants |
| 04/10/2001 | US6214719 Method of implementing air-gap technology for low capacitance ILD in the damascene scheme |
| 04/10/2001 | US6214718 Semiconductor assembling method and apparatus |
| 04/10/2001 | US6214717 Method for adding plasma treatment on bond pad to prevent bond pad staining problems |
| 04/10/2001 | US6214715 Method for fabricating a self aligned contact which eliminates the key hole problem using a two step spacer deposition |
| 04/10/2001 | US6214714 Forming titanium film on substrate, forming intermediate layer comprising silicon on titanium film, forming titanium nitride film on intermediate layer, wherein intermediate layer protects titanium film from chemical attack during process |
| 04/10/2001 | US6214713 Two step cap nitride deposition for forming gate electrodes |
| 04/10/2001 | US6214712 Heating semiconductor surface and introducing hydrogen gas into high vacuum environment to develop conditions favorable for growing desired metal oxide, yet unfavorable for formation of any native oxides |
| 04/10/2001 | US6214711 Method of low angle, low energy physical vapor of alloys including redepositing layers of different compositions in trenches |
| 04/10/2001 | US6214710 Depositing thin buffer layer of zirconium or hafnium over conductive regions reduces formation of native oxide on surface, provides smooth interface of resulting silicide with underlying silicon |
| 04/10/2001 | US6214709 Method of fabricating self-aligned silicide |
| 04/10/2001 | US6214708 Method and apparatus for diffusing zinc into groups III-V compound semiconductor crystals |
| 04/10/2001 | US6214707 Method of forming a doped region in a semiconductor substrate |
| 04/10/2001 | US6214706 Hot wire chemical vapor deposition method and apparatus using graphite hot rods |
| 04/10/2001 | US6214705 Method for fabricating a gate eletrode |
| 04/10/2001 | US6214704 Method of processing semiconductor wafers to build in back surface damage |
| 04/10/2001 | US6214703 Method to increase wafer utility by implementing deep trench in scribe line |
| 04/10/2001 | US6214702 Methods of forming semiconductor substrates using wafer bonding techniques and intermediate substrates formed thereby |
| 04/10/2001 | US6214701 Semiconductor substrate and thin film semiconductor device, method of manufacturing the same, and anodizing apparatus |
| 04/10/2001 | US6214700 Semiconductor device and method for producing same |
| 04/10/2001 | US6214699 Method for forming an isolation structure in a substrate |
| 04/10/2001 | US6214698 Growing undoped silicon glass liner to coat bottom surface and side walls of trench formed in substrate, depositing undoped silicon oxide layer, depositing boron doped silicon oxide layer to fill trench, heating to reflow to fill any voids |
| 04/10/2001 | US6214697 Trench isolation for semiconductor devices |
| 04/10/2001 | US6214696 Method of fabricating deep-shallow trench isolation |
| 04/10/2001 | US6214695 Method of manufacturing semiconductor device |
| 04/10/2001 | US6214694 Process of making densely patterned silicon-on-insulator (SOI) region on a wafer |
| 04/10/2001 | US6214693 Process for the production of semiconductor device |
| 04/10/2001 | US6214691 Method for forming shallow trench isolation |
| 04/10/2001 | US6214690 Method of forming a semiconductor device having integrated electrode and isolation region formation |
| 04/10/2001 | US6214689 Apparatus for manufacturing semiconductor device, method of manufacturing capacitor of semiconductor device thereby, and resultant capacitor |
| 04/10/2001 | US6214688 Methods of forming integrated circuit capacitors having U-shaped electrodes |
| 04/10/2001 | US6214687 Method of forming a capacitor and a capacitor construction |
| 04/10/2001 | US6214686 Spatially offset deep trenches for high density DRAMS |
| 04/10/2001 | US6214684 Method of forming a semiconductor device using an excimer laser to selectively form the gate insulator |
| 04/10/2001 | US6214683 Forming hard-mask by lithography, selectively oxidizing metal layer situated between etch-stop and oxidation resistant layers to reduce lateral dimension of mask, removing etch-stop and oxidation resistant layers, using residue as mask |
| 04/10/2001 | US6214682 Forming screen oxide layer on substrate having gate oxide and electrode, implanting p-type impurity ions into substrate through oxide to form lightly doped source and drain regions, performing rapid thermal anneal in nitrogen atmosphere |
| 04/10/2001 | US6214681 Utilizing semiconductor and germanium sources to provide thin film above top surface of substrate, reducing germanium source while utilizing semiconductor source to form buffer layer, oxidizing buffer layer, providing spacers on side walls |
| 04/10/2001 | US6214680 Method to fabricate a sub-quarter-micron MOSFET with lightly doped source/drain regions |
| 04/10/2001 | US6214679 Forming silicon germanium alloy on substrate, forming cobalt film on said alloy, heating to temperature greater than 850 degrees c. for period of time less than 20 seconds to form cobaltdigermanosilicide film |
| 04/10/2001 | US6214678 Minimizing residual surface charge by heating substrate to oxide desorption temperature, growing layers of compounds by metal organic chemical vapor deposition on substrate at growth temperature equal to oxide desorption temperature |
| 04/10/2001 | US6214677 Method of fabricating self-aligned ultra short channel |
| 04/10/2001 | US6214676 Embedded memory logic device using self-aligned silicide and manufacturing method therefor |
| 04/10/2001 | US6214675 Method for fabricating a merged integrated circuit device |
| 04/10/2001 | US6214674 Method of fabricating high voltage device suitable for low voltage device |
| 04/10/2001 | US6214673 Process for forming vertical semiconductor device having increased source contact area |
| 04/10/2001 | US6214672 Method for manufacturing two-bit flash memory |
| 04/10/2001 | US6214671 Method of forming dual gate structure |
| 04/10/2001 | US6214670 Method for manufacturing short-channel, metal-gate CMOS devices with superior hot carrier performance |
| 04/10/2001 | US6214669 Single-chip contact-less read-only memory (ROM) device and the method for fabricating the device |
| 04/10/2001 | US6214668 Structure of a channel write/erase flash memory cell and manufacturing method and operating method thereof |
| 04/10/2001 | US6214667 Method for fabricating a flash memory |
| 04/10/2001 | US6214666 Method of forming a non-volatile memory device |
| 04/10/2001 | US6214665 Semiconductor memory device having memory cells each having a conductive body of booster plate and a method for manufacturing the same |
| 04/10/2001 | US6214664 Method of manufacturing semiconductor device |
| 04/10/2001 | US6214663 Methods of fabricating integrated circuit devices having contact pads which are separated by sidewall spacers |
| 04/10/2001 | US6214662 Forming self-align source line for memory array |
| 04/10/2001 | US6214661 Method to prevent oxygen out-diffusion from BSTO containing micro-electronic device |
| 04/10/2001 | US6214660 Capacitor for integrated circuit and its fabrication method |
| 04/10/2001 | US6214659 Forming deep ultraviolet photoresist layer having cylindrical structure using only one mask; forming conductive layer, main structure of bottom electrode, on sidewall of photoresist layer by silylation |
| 04/10/2001 | US6214658 Self-aligned contact structure and method |
| 04/10/2001 | US6214657 Semiconductor device isolation structure and fabrication method of semiconductor device using the same |
| 04/10/2001 | US6214656 Partial silicide gate in sac (self-aligned contact) process |
| 04/10/2001 | US6214655 Amorphous silicon disposable spacer to reduce mask count in CMOS transistor formation |
| 04/10/2001 | US6214654 Method for forming super-steep retrograded channel (SSRC) for CMOS transistor using rapid laser annealing to reduce thermal budget |
| 04/10/2001 | US6214653 Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate |
| 04/10/2001 | US6214652 Forming thin film transistor layer of polycrystalline material on substrate, masking portion of thin film, conducting germanium implant into unmasked portion of thin film comprising drain offset region |
| 04/10/2001 | US6214650 Method and apparatus for sealing a ball grid array package and circuit card interconnection |
| 04/10/2001 | US6214649 Integrated circuit package |
| 04/10/2001 | US6214648 Semiconductor chip package and method for fabricating the same |
| 04/10/2001 | US6214646 Soldering optical subassemblies |
| 04/10/2001 | US6214645 Method of molding ball grid array semiconductor packages |
| 04/10/2001 | US6214644 Flip-chip micromachine package fabrication method |
| 04/10/2001 | US6214643 Stress reduction for flip chip package |
| 04/10/2001 | US6214642 Area array stud bump flip chip device and assembly process |
| 04/10/2001 | US6214640 Method of manufacturing a plurality of semiconductor packages |
| 04/10/2001 | US6214639 Method of producing a semiconductor device |
| 04/10/2001 | US6214637 Method of forming a photoresist pattern on a semiconductor substrate using an anti-reflective coating deposited using only a hydrocarbon based gas |
| 04/10/2001 | US6214635 Method and apparatus for underfill of bumped or raised die |
| 04/10/2001 | US6214630 Wafer level integrated circuit structure and method of manufacturing the same |
| 04/10/2001 | US6214526 Semiconductor processing using antireflective layer having high wet etch rate |
| 04/10/2001 | US6214525 Printed circuit board with circuitized cavity and methods of producing same |
| 04/10/2001 | US6214524 Integrated circuit prepared with a step for neutralization of excess acids generated by photoacid generator after photolithography by exposing developed photoresist to amine, aldehyde, amide, or nitrogen; by-product inhibition |