Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2001
05/03/2001WO2001031705A1 Methods for forming co-axial interconnect in a cmos process
05/03/2001WO2001031702A1 Method for protecting integrated card chips by deposit of an electrically insulating layer by vacuum suction
05/03/2001WO2001031701A1 Method for suppressing narrow width effects in cmos technology
05/03/2001WO2001031700A1 Wafer holder and epitaxial growth device
05/03/2001WO2001031699A1 Advanced flip-chip join package
05/03/2001WO2001031698A2 Method for thermally treating semiconductor substrates
05/03/2001WO2001031697A1 Plasma treatment for polymer removal after via etch
05/03/2001WO2001031696A1 Composition for chemical purification of surfaces off adsorbed metal ions and atoms
05/03/2001WO2001031695A1 High temperature oxide deposition for eeprom devices
05/03/2001WO2001031694A1 Apparatus for manufacturing semiconductor device
05/03/2001WO2001031693A1 Method and apparatus for monitoring process exhaust gas, semiconductor-manufacturing device, and method and system for managing semiconductor-manufacturing device
05/03/2001WO2001031692A1 Method for manufacturing a capacitor by forming a silicon eletrode having hemispherical silicon
05/03/2001WO2001031691A1 Method and apparatus for cleaning a semiconductor wafer
05/03/2001WO2001031690A1 Transport device
05/03/2001WO2001031689A1 Method and device for thermal treatment of substrates
05/03/2001WO2001031685A2 InPSb/InAs BJT DEVICE AND METHOD OF MAKING
05/03/2001WO2001031683A1 Plasma doping system comprising a hollow cathode
05/03/2001WO2001031682A1 Method and apparatus for low voltage plasma doping using dual pulses
05/03/2001WO2001031681A1 Method and apparatus for eliminating displacement current from current measurements in a plasma processing system
05/03/2001WO2001031679A1 Wide parameter range ion beam scanners
05/03/2001WO2001031404A1 Using block copolymers as supercritical fluid developable photoresists
05/03/2001WO2001031294A1 Optical measurements of patterned structures
05/03/2001WO2001031092A2 Method, chemistry, and apparatus for noble metal electroplating a on a microelectronic workpiece
05/03/2001WO2001030715A1 Fluoride gas etching of silicon with improved selectivity
05/03/2001WO2001030541A1 Apparatus for gripping microplates
05/03/2001WO2001030530A1 An apparatus and method for laser welding of ribbons for electrical connections
05/03/2001WO2001004931A3 Method and apparatus for providing uniform gas delivery to substrates in cvd and pecvd processes
05/03/2001WO2001004567A3 Method and apparatus for three dimensional inspection of electronic components
05/03/2001WO2001001485A3 A semiconductor device
05/03/2001WO2001001460A3 Temperature controlled wafer chuck
05/03/2001WO2001000522A3 Nanometer-scale modulation
05/03/2001WO2000075965A3 Power mosfet and method of making the same
05/03/2001US20010000775 Carrier head with a flexible membrane for a chemical mechanical polishing system
05/03/2001US20010000773 Method for determining a polishing recipe based upon the measured pre-polish thickness of a process layer
05/03/2001US20010000772 Method and apparatus for uniformly planarizing a microelectronic substrate
05/03/2001US20010000761 Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants
05/03/2001US20010000760 Method for forming an integrated circuit interconnect using a dual poly process
05/03/2001US20010000759 Substrate handling chamber
05/03/2001US20010000758 Method of programming a semiconductor memory
05/03/2001US20010000757 Semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location, forming an electrical interconnection with a transistor source/ drain region, and integrated circuitry
05/03/2001US20010000756 Having a polycrystalline channel and a drain offset area also polycrystalline but of a larger grain size formed by recrystallization of the drain offset area after implanting amorphous silicon; static random memory cells; no leakage
05/03/2001US20010000755 Covering electrodes with an insulating layer, and planarizing electrodes and insulating layer so that they become flush with each other, filling boundary portions between electrodes; prevents alignment failures of liquid crystal
05/03/2001US20010000754 Where a resin supply control means controls the amount of resin so more resin is supplied near a central portion of the semiconductor chip than near end portions of the semiconductor chip to fill gap between chip and mount board
05/03/2001US20010000753 Apparatus and method for chemical/mechanical polishing
05/03/2001US20010000747 Multi-function chamber for a substrate processing system
05/03/2001US20010000733 Method of manufacturing nitride system III-V compound layer and method of manufacturing substrate
05/03/2001US20010000721 Wafer handling robot having X-Y stage for wafer handling and positioning
05/03/2001US20010000720 Dual arm linear hand-off wafer transfer assembly
05/03/2001US20010000691 Semiconductor integrated circuit device
05/03/2001US20010000689 Semiconductor memory device
05/03/2001US20010000688 Memory structure in ferroelectric nonvolatile memory and readout method therefor
05/03/2001US20010000687 Semiconductor device
05/03/2001US20010000679 Sample inspection system
05/03/2001US20010000676 Integral-type liquid crystal panel with image sensor function
05/03/2001US20010000646 Test system with mechanical alignment for semiconductor chip scale packages and dice
05/03/2001US20010000632 Semiconductor device and method for manufacturing the same
05/03/2001US20010000631 Chip scale surface mount package for semiconductor device and process of fabricating the same
05/03/2001US20010000629 Semiconductor device and process of producing the same
05/03/2001US20010000628 Compact SOI body contact link
05/03/2001US20010000626 Method for forming a non-volatile memory cell that eliminates substrate trenching
05/03/2001US20010000625 Non-volatile semiconductor memory device and its manufacturing method
05/03/2001US20010000624 Microelectronic devices including ferroelectric capacitors with lower electrodes extending into contact holes and related methods
05/03/2001US20010000620 Thin film transistor and method of fabricating the same
05/03/2001US20010000613 Feed unit for moving parts
05/03/2001US20010000603 Magnetoresistive (MR) sensor element with sunken lead structure
05/03/2001US20010000586 Chemical mechanically polishing the silicon layer with an oxide polishing slurry, then the silicon layer is chemical mechanically polished with a silicon-polishing slurry until the substrate is planarized
05/03/2001US20010000581 Method of manufacturing laminated ceramic electronic parts
05/03/2001US20010000575 Transferring a substrate through the cleaning or etching liquid at a level underneath the surface of the liquid making use of cleaning and etching tank with inlet/outlet openings and contains liquid cleaner installed in gaseous environment
05/03/2001DE19954319C1 Production of multilayered contact electrodes used in diodes comprises applying a first metallizing layer, heat treating and applying a second metallizing layer over the first layer
05/03/2001DE19952374A1 Lamp for heating devices used for thermal treatment of semiconductor substrates has cylindrical glass body with base at each end of glass body
05/03/2001DE19951945A1 Semiconductor component with metallized sidewalls on silicon wafer power components has a metal edging surrounding the components on an underside and on partially covered metal sidewalls and deep troughs etched on silicon wafers.
05/03/2001DE19951164A1 Folienverbund Film composite
05/03/2001DE19951017A1 Verfahren und Vorrichtung zur Plasmabehandlung von Oberflächen Method and apparatus for plasma treatment of surfaces
05/03/2001DE19950563A1 Verfahren zur Reinigung einer monokristallinen Silizium-Halbleiterscheibe A method for cleaning a monocrystalline silicon wafer
05/03/2001DE19950540A1 Verfahren zur Herstellung einer Kondensator-Elektrode mit Barrierestruktur A method for producing a capacitor electrode having a barrier structure
05/03/2001DE19949993C1 Microcontact printing process, for structuring oxidized surfaces using stamp in microelectronics, comprises wetting surface of stamp with silane or thiol molecules before contacting the stamp with oxidized surfaces
05/03/2001DE19948906A1 Deep-diffused n-conducting region production in p-doped silicon substrate comprises ion implanting sulfur or selenium as n-foreign material into regions and subsequently heat treating
05/03/2001DE19948630A1 Verfahren und Vorrichtung zum Behandeln von Substraten Method and apparatus for treating substrates
05/03/2001DE19948555A1 Semiconductor chip manufacturing method has contact elements for connecting chip to external electrical components provided before separation of chip from semiconductor wafer
05/03/2001DE19948382A1 Detektor für grosse Waferflächen Detector for large wafer surfaces
05/03/2001DE19946753A1 Method of detecting and preventing regions critical for etching, e.g. for screen printing plate manufacture
05/03/2001DE19946715C1 Verfahren zur dreidimensionalen Integration mikroelektronischer Systeme A method for three-dimensional integration of microelectronic systems
05/03/2001DE19944306A1 Reduzierung der Kopplung zwischen Halbleitersubstrat und darauf integrierter Spule Reducing the coupling between the semiconductor substrate and integrated coil
05/03/2001DE10054142A1 Roughness measuring method of wafer surface, by measuring selected area containing majority of points on wafer surface using atomic force microscope to measure microroughness
05/03/2001DE10053463A1 Semiconductor substrate comprises substrate component of one conductivity type with channels which taper from top to bottom and are deeper than their width and which are filled with semiconductor of opposite type to first component
05/03/2001DE10053207A1 Design validation method for integrated system chip circuit, involves validating entire design using simulation test banks of complete system chip and execution of application
05/03/2001DE10051933A1 Reaction chamber for molding semiconductor wafer, comprises chamber body with chamber for semiconductor wafer, through-holes in wall of chamber body and temperature sensors arranged in through-holes
05/03/2001DE10046067A1 Phasenschiebungsmaske sowie Verfahren zur Herstellung derselben Phase shift mask and method of manufacturing the same
05/03/2001DE10043904A1 Semiconductor device such as vertical mold field effect transistor, has source diffusion layer formed on upper portion of base diffusion layer provided on both sides of gate polysilicon layer
05/03/2001DE10038219A1 Cleaning device and treatment method for preventing oxidation in metal wire coating has a treatment cleaning container, a fluid reservoir to store cleaning fluid, feeder pipes to supply cleaning fluid and return-flow pipes.
05/03/2001DE10036867A1 Method for processing substrate, e.g. semiconductor wafer comprises arranging substrate in processing vessel, forming layer of solvent over surface of substrate, and dissolving an operating gas in layer of solvent
05/03/2001DE10007439A1 Apparatus for cleaning substrates especially semiconductor wafers
05/02/2001EP1096576A1 Semiconductor device
05/02/2001EP1096575A1 Non-volatile memory cell with a single level of polysilicon and corresponding manufacturing process
05/02/2001EP1096572A1 Electrically programmable and erasable memory device and method of operating same
05/02/2001EP1096570A1 Semiconductor device having a ferroelectric capacitor and a fabrication process thereof
05/02/2001EP1096568A2 Display apparatus and method for fabricating the same
05/02/2001EP1096567A2 BGA package and method for fabricating the same
05/02/2001EP1096565A2 Sealed-by-resin type semiconductor device and liquid crystal display module including the same
05/02/2001EP1096563A2 Semiconductor package with premolded parts