Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2001
05/01/2001US6225205 Method of forming bump electrodes
05/01/2001US6225204 Method for preventing poisoned vias and trenches
05/01/2001US6225203 PE-SiN spacer profile for C2 SAC isolation window
05/01/2001US6225202 Selective etching of unreacted nickel after salicidation
05/01/2001US6225201 Ultra short transistor channel length dictated by the width of a sidewall spacer
05/01/2001US6225199 Semiconductor device having triple-well
05/01/2001US6225198 Process for forming shaped group II-VI semiconductor nanocrystals, and product formed using process
05/01/2001US6225197 Method of forming polycrystalline film by steps including introduction of nickel and rapid thermal anneal
05/01/2001US6225196 High electron mobility transistor and method of fabricating the same
05/01/2001US6225195 Method for manufacturing group III-V compound semiconductor
05/01/2001US6225194 Process for producing chip and pressure sensitive adhesive sheet for said process
05/01/2001US6225193 Method of cleaving a semiconductor wafer including implanting and annealing resulting in exfoliation
05/01/2001US6225192 Method of producing a thin layer of semiconductor material
05/01/2001US6225191 The cleaning operation is performed in situ after the wafer is diced and while the diced chips are still affixed to the tape carrier.
05/01/2001US6225190 Process for the separation of at least two elements of a structure in contact with one another by ion implantation
05/01/2001US6225189 Method of fabricating shallow trench isolation structure
05/01/2001US6225188 Self aligned method for differential oxidation rate at shallow trench isolation edge
05/01/2001US6225187 Method for STI-top rounding control
05/01/2001US6225186 Method for fabricating LOCOS isolation
05/01/2001US6225185 Method for fabricating semiconductor memory having good electrical characteristics and high reliability
05/01/2001US6225184 Semiconductor device manufacturing method
05/01/2001US6225183 Method of fabricating a thin-film resistor having stable resistance
05/01/2001US6225182 Simplified high Q inductor substrate
05/01/2001US6225181 Trench isolated bipolar transistor structure integrated with CMOS technology
05/01/2001US6225180 Semiconductor device and method of manufacturing the same
05/01/2001US6225179 Semiconductor integrated bi-MOS circuit having isolating regions different in thickness between bipolar area and MOS area and process of fabrication thereof
05/01/2001US6225178 Radiation hardened field oxide for VLSI sub-micron MOS device
05/01/2001US6225177 Electrode resistance improved MOSFET with source and drain regions reduced in size beyond lithography limit and method for making the same
05/01/2001US6225176 Step drain and source junction formation
05/01/2001US6225175 Process for defining ultra-thin geometries
05/01/2001US6225174 Method for forming a spacer using photosensitive material
05/01/2001US6225173 Recessed channel structure for manufacturing shallow source/drain extensions
05/01/2001US6225172 Integrated circuitry and method of forming a field effect transistor
05/01/2001US6225171 Shallow trench isolation process for reduced for junction leakage
05/01/2001US6225170 Self-aligned damascene gate with contact formation
05/01/2001US6225169 High density plasma nitridation as diffusion barrier and interface defect densities reduction for gate dielectric
05/01/2001US6225168 Highly reliable semiconductor device having an increased operating speed as compared to conventional transistors.
05/01/2001US6225167 Method of generating multiple oxide thicknesses by one oxidation step using NH3 nitridation followed by re-oxidation
05/01/2001US6225166 Method of manufacturing electrostatic discharge protective circuit
05/01/2001US6225164 Semiconductor memory and method for fabricating the same
05/01/2001US6225163 Process for forming high quality gate silicon dioxide layers of multiple thicknesses
05/01/2001US6225161 Fully recessed semiconductor method for low power applications with single wrap around buried drain region
05/01/2001US6225160 Method of manufacturing bottom electrode of capacitor
05/01/2001US6225159 Cell capacitors, memory cells, memory arrays, and method of fabrication
05/01/2001US6225158 Trench storage dynamic random access memory cell with vertical transfer device
05/01/2001US6225157 Capacitor/antifuse structure having a barrier-layer electrode and improved barrier layer
05/01/2001US6225156 Ferroelectric integrated circuit having low sensitivity to hydrogen exposure and method for fabricating same
05/01/2001US6225155 Method of forming salicide in embedded dynamic random access memory
05/01/2001US6225154 Bonding of silicon wafers
05/01/2001US6225152 Semiconductor device and fabrication method thereof
05/01/2001US6225151 Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion
05/01/2001US6225150 Method for forming a TFT in a liquid crystal display
05/01/2001US6225149 Methods to fabricate thin film transistors and circuits
05/01/2001US6225148 Method of fabricating semiconductor device
05/01/2001US6225147 Methods of forming ICS conductive lines, a conductive grid, a conductive network, an electrical interconnection to a node location, an electrical interconnection with a transistor source/drain region and ICS
05/01/2001US6225145 Method of fabricating vacuum micro-structure
05/01/2001US6225144 Method and machine for underfilling an assembly to form a semiconductor package
05/01/2001US6225137 Semiconductor wafer evaluation method
05/01/2001US6225135 In-situ method for real time monitoring of chemical baths for transition metals with multi-channel electrodes
05/01/2001US6225133 Method of manufacturing thin film capacitor
05/01/2001US6225059 Advanced active electronic devices including collection electrodes for molecular biological analysis and diagnostics
05/01/2001US6225033 In which slits having a rectangular cross section can be formed and the exposure dose and the focusing margin can be sufficiently large.
05/01/2001US6225031 That avoids introducing dimensional changes and does not adversely impact the dimensional stability
05/01/2001US6225028 Fiberglass-reinforced epoxy resins, fr4, or polytetrafluorethylene (e.g., teflon), in lieu of ceramic materials.
05/01/2001US6225025 Fabrication process of a semiconductor device by electron-beam lithography
05/01/2001US6225020 Such as used in 4 g or 16 g dram semiconductor devices using a light source such as arf, an e-beam, euv, or an ion beam, photoresist for the top surface image (tsi) process using silylation, maleimide andnorbonene carboxylate comonomers,
05/01/2001US6225019 Photosensitive resin, resist based on the photosensitive resin, exposure apparatus and exposure method using the resist, and semiconductor device obtained by the exposure method
05/01/2001US6225011 Method for manufacturing semiconductor devices utilizing plurality of exposure systems
05/01/2001US6224950 Method for formation of thin film
05/01/2001US6224942 Alloy of aluminum and titanium layering with higher melting point; layers are formed, photpatterned into a conductive line used in semiconductor processing of integrated circuitry
05/01/2001US6224934 Measuring ultraviolet rays
05/01/2001US6224810 Injection of plastics, projection the eject pin into the mold cavity and joining then shrinkage
05/01/2001US6224785 Aqueous ammonium fluoride and amine containing compositions for cleaning inorganic residues on semiconductor substrates
05/01/2001US6224737 Immersing semiconductor into electroplating solution containing predetermined concentration of brighteners and levelers
05/01/2001US6224724 Physical vapor processing of a surface with non-uniformity compensation
05/01/2001US6224713 Method and apparatus for ultrasonic wet etching of silicon
05/01/2001US6224712 Polishing apparatus
05/01/2001US6224711 Assembly process for flip chip package having a low stress chip and resulting structure
05/01/2001US6224703 Method of making laminate ceramic substrate with domed pads
05/01/2001US6224690 Copper-free layer of nickel, cobalt, iron or alloys thereof; solder balls of tin and bismuth, silver, and/or antimony; avoids alpha-particle emission and soft logic errors
05/01/2001US6224682 CVD of metals capable of receiving nickel or alloys thereof using inert contact
05/01/2001US6224681 Vaporizing reactant liquids for chemical vapor deposition film processing
05/01/2001US6224680 Wafer transfer system
05/01/2001US6224679 Controlling gas in a multichamber processing system
05/01/2001US6224677 Gas recovery unit utilizing dual use of gas
05/01/2001US6224676 Gas supply apparatus and film forming apparatus
05/01/2001US6224675 Multiple head dispensing system and method
05/01/2001US6224674 Seal coating mask for semiconductor element and method of use thereof
05/01/2001US6224670 Cup-type plating method and cleaning apparatus used therefor
05/01/2001US6224669 Method for fabricating a semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon
05/01/2001US6224668 Method for producing SOI substrate and SOI substrate
05/01/2001US6224667 Method for fabricating semiconductor light integrated circuit
05/01/2001US6224638 Method and apparatus for scheduling wafer processing within a multiple chamber semiconductor wafer processing tool having a multiple blade robot
05/01/2001US6224472 Retaining ring for chemical mechanical polishing
05/01/2001US6224470 Pad cleaning brush for chemical mechanical polishing apparatus and method of making the same
05/01/2001US6224466 Methods of polishing materials, methods of slowing a rate of material removal of a polishing process
05/01/2001US6224465 Methods and apparatus for chemical mechanical planarization using a microreplicated surface
05/01/2001US6224464 Polishing method and polisher used in the method
05/01/2001US6224461 Method and apparatus for stabilizing the process temperature during chemical mechanical polishing
05/01/2001US6224459 Workpiece inspection and handling