| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 04/03/2001 | US6211568 Comprising: an insulating layer on a silicon substrate; a contact hole, a ptsi layer, a tiw layer, a tiw(n) layer, an au layer; very stable diffusion barrier by using a nitrided tiw, tiw(n); improved adhesion strength and step coverage |
| 04/03/2001 | US6211561 Interconnect structure and method employing air gaps between metal lines and between metal layers |
| 04/03/2001 | US6211559 Symmetric magnetic tunnel device |
| 04/03/2001 | US6211557 Contact structure using taper contact etching and polycide step |
| 04/03/2001 | US6211556 Eliminating buried contact trench in MOSFET devices having self-aligned silicide |
| 04/03/2001 | US6211555 Semiconductor device with a pair of transistors having dual work function gate electrodes |
| 04/03/2001 | US6211553 Thin-film transistor, a method for manufacturing same, and a liquid crystal display device using the transistor |
| 04/03/2001 | US6211552 Resurf LDMOS device with deep drain region |
| 04/03/2001 | US6211550 Backmetal drain terminal with low stress and thermal resistance |
| 04/03/2001 | US6211549 High breakdown voltage semiconductor device including first and second semiconductor elements |
| 04/03/2001 | US6211548 Metal-gate non-volatile memory cell |
| 04/03/2001 | US6211547 Semiconductor memory array with buried drain lines and processing methods therefor |
| 04/03/2001 | US6211546 Method of manufacturing nonvolatile semiconductor memory device |
| 04/03/2001 | US6211545 Device fabricated by a method of controlling outdiffusion from a doped three-dimensional film |
| 04/03/2001 | US6211544 Memory cell layout for reduced interaction between storage nodes and transistors |
| 04/03/2001 | US6211543 Lead silicate based capacitor structures |
| 04/03/2001 | US6211542 Completely encapsulated top electrode of a ferroelectric capacitor using a lead-enhanced escapsulation layer |
| 04/03/2001 | US6211536 Semiconductor device having improved crystal orientation |
| 04/03/2001 | US6211535 Method of manufacturing a semiconductor device |
| 04/03/2001 | US6211534 Thin film transistor array and method for fabricating the same |
| 04/03/2001 | US6211533 Solid state imager including TFTs with variably doped contact layer system for reducing TFT leakage current and increasing mobility |
| 04/03/2001 | US6211531 Controllable conduction device |
| 04/03/2001 | US6211530 Sparse-carrier devices and method of fabrication |
| 04/03/2001 | US6211528 Electron beam drawing method in which cell projection manner and variably shaped beam manner are used in combination |
| 04/03/2001 | US6211527 Method for device editing |
| 04/03/2001 | US6211514 Device and method for sensing wafer-shaped objects and shelves in a container |
| 04/03/2001 | US6211495 Temperature control system for a thermal reactor |
| 04/03/2001 | US6211488 Method and apparatus for separating non-metallic substrates utilizing a laser initiated scribe |
| 04/03/2001 | US6211469 Printed circuit substrate with comb-type electrodes capable of improving the reliability of the electrode connections |
| 04/03/2001 | US6211468 Flexible circuit with conductive vias having off-set axes |
| 04/03/2001 | US6211461 Chip size package and method of fabricating the same |
| 04/03/2001 | US6211455 Silicon thin-film, integrated solar cell, module, and methods of manufacturing the same |
| 04/03/2001 | US6211443 Soybean cultivar 9581419733880 |
| 04/03/2001 | US6211328 Phenol resin |
| 04/03/2001 | US6211127 Containing alkanolamine, sulfone or sulfoxide and glycol ether |
| 04/03/2001 | US6211126 Formulations including a 1, 3-dicarbonyl compound chelating agent for stripping residues from semiconductor substrates |
| 04/03/2001 | US6211098 Wet oxidation method for forming silicon oxide dielectric layer |
| 04/03/2001 | US6211097 Planarization process |
| 04/03/2001 | US6211096 Tunable dielectric constant oxide and method of manufacture |
| 04/03/2001 | US6211095 Method for relieving lattice mismatch stress in semiconductor devices |
| 04/03/2001 | US6211094 Thickness control method in fabrication of thin-film layers in semiconductor devices |
| 04/03/2001 | US6211093 Laser ablative removal of photoresist |
| 04/03/2001 | US6211092 Counterbore dielectric plasma etch process particularly useful for dual damascene |
| 04/03/2001 | US6211091 Self-aligned eetching process |
| 04/03/2001 | US6211090 Method of fabricating flux concentrating layer for use with magnetoresistive random access memories |
| 04/03/2001 | US6211089 Method for fabricating GaN substrate |
| 04/03/2001 | US6211088 Manufacturing method for semiconductor gas-phase epitaxial wafer |
| 04/03/2001 | US6211087 Chemical wet etch removal of underlayer material after performing chemical mechanical polishing on a primary layer |
| 04/03/2001 | US6211086 Method of avoiding CMP caused residue on wafer edge uncompleted field |
| 04/03/2001 | US6211085 Method of preparing CU interconnect lines |
| 04/03/2001 | US6211084 Method of forming reliable copper interconnects |
| 04/03/2001 | US6211083 Use of a novel capped anneal procedure to improve salicide formation |
| 04/03/2001 | US6211082 Chemical vapor deposition of tungsten using nitrogen-containing gas |
| 04/03/2001 | US6211081 Method of manufacturing a semiconductor device in a CVD reactive chamber |
| 04/03/2001 | US6211079 Method for fabricating interconnects of a dynamic random access memory (DRAM) |
| 04/03/2001 | US6211078 Method of improving resist adhesion for use in patterning conductive layers |
| 04/03/2001 | US6211077 Method for forming polycrystal silicon film for semiconductor elements |
| 04/03/2001 | US6211076 Bus line wiring structure in a semiconductor device and method of manufacturing the same |
| 04/03/2001 | US6211075 Method of improving metal stack reliability |
| 04/03/2001 | US6211074 Methods and arrangements for reducing stress and preventing cracking in a silicide layer |
| 04/03/2001 | US6211073 Methods for making copper and other metal interconnections in integrated circuits |
| 04/03/2001 | US6211072 Fabricating a titanium nitride layer on an underlying structure. tetrakis-dimethyl-amino-titanium vapor is decomposed to deposit a layer containing titanium nitride, |
| 04/03/2001 | US6211071 Optimized trench/via profile for damascene filling |
| 04/03/2001 | US6211070 Peripheral structure of a chip as a semiconductor device, and manufacturing method thereof |
| 04/03/2001 | US6211069 Dual damascene process flow for a deep sub-micron technology |
| 04/03/2001 | US6211068 Dual damascene process for manufacturing interconnects |
| 04/03/2001 | US6211067 Method for manufacturing metal plug |
| 04/03/2001 | US6211066 Electronic devices with barium barrier film and process for making same |
| 04/03/2001 | US6211065 Method of depositing and amorphous fluorocarbon film using HDP-CVD |
| 04/03/2001 | US6211064 Method for fabricating CMOS device |
| 04/03/2001 | US6211063 Method to fabricate self-aligned dual damascene structures |
| 04/03/2001 | US6211062 Method for manufacturing semiconductor device having multiple wiring layer |
| 04/03/2001 | US6211061 Dual damascene process for carbon-based low-K materials |
| 04/03/2001 | US6211060 Method for planarizing a damascene structure |
| 04/03/2001 | US6211059 Method of manufacturing semiconductor device having contacts with different depths |
| 04/03/2001 | US6211058 Semiconductor device with multiple contact sizes |
| 04/03/2001 | US6211057 Method for manufacturing arch air gap in multilevel interconnection |
| 04/03/2001 | US6211056 Integrated circuit air bridge structures and methods of fabricating same |
| 04/03/2001 | US6211055 Wet-dry-wet process in wet station |
| 04/03/2001 | US6211054 Method of forming a conductive line and method of forming a local interconnect |
| 04/03/2001 | US6211053 Laser wire bonding for wire embedded dielectrics to integrated circuits |
| 04/03/2001 | US6211052 Mask repattern process |
| 04/03/2001 | US6211051 Reduction of plasma damage at contact etch in MOS integrated circuits |
| 04/03/2001 | US6211050 Fill pattern in kerf areas to prevent localized non-uniformities of insulating layers at die corners on semiconductor substrates |
| 04/03/2001 | US6211049 Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals |
| 04/03/2001 | US6211048 Method of reducing salicide lateral growth |
| 04/03/2001 | US6211047 Method for forming contact of semiconductor device |
| 04/03/2001 | US6211046 Method of manufacturing a semiconductor device |
| 04/03/2001 | US6211045 Nitrogen dioxide, nitrogen monoxide |
| 04/03/2001 | US6211044 Process for fabricating a semiconductor device component using a selective silicidation reaction |
| 04/03/2001 | US6211043 Thermal decomposition of a metal organic compound and a solar cell using the above thin film, metal sulfide thin films of high purity, density and quality for photoelectric devices or solarcells |
| 04/03/2001 | US6211042 Growth of epitaxial semiconductor films in presence of reactive metal |
| 04/03/2001 | US6211041 Silicon-on-insulator (SOI) substrate and method of fabricating the same |
| 04/03/2001 | US6211040 Two-step, low argon, HDP CVD oxide deposition process |
| 04/03/2001 | US6211039 Silicon-on-insulator islands and method for their formation |
| 04/03/2001 | US6211038 Semiconductor device, and method for manufacturing the same |
| 04/03/2001 | US6211037 Locos processes |
| 04/03/2001 | US6211036 Semiconductor device having an improved capacitor structure, and a method of manufacturing the same |
| 04/03/2001 | US6211035 Integrated circuit and method |
| 04/03/2001 | US6211034 Metal patterning with adhesive hardmask layer |