| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 07/17/2001 | US6261969 Method of manufacturing semiconductor apparatus and apparatus thereof |
| 07/17/2001 | US6261968 Method of forming a self-aligned contact hole on a semiconductor wafer |
| 07/17/2001 | US6261967 Easy to remove hard mask layer for semiconductor device fabrication |
| 07/17/2001 | US6261966 Method for improving trench isolation |
| 07/17/2001 | US6261965 Effective removal of undesirably formed silicon carbide during the manufacture of semiconductor device |
| 07/17/2001 | US6261964 Material removal method for forming a structure |
| 07/17/2001 | US6261963 Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices |
| 07/17/2001 | US6261962 Method of surface treatment of semiconductor substrates |
| 07/17/2001 | US6261961 Adhesion layer for etching of tracks in nuclear trackable materials |
| 07/17/2001 | US6261960 High density contacts having rectangular cross-section for dual damascene applications |
| 07/17/2001 | US6261957 Self-planarized gap-filling by HDPCVD for shallow trench isolation |
| 07/17/2001 | US6261955 Spraying; complexing, metallization to form volatile compound; flushing |
| 07/17/2001 | US6261954 Method to deposit a copper layer |
| 07/17/2001 | US6261953 Method of forming a copper oxide film to etch a copper surface evenly |
| 07/17/2001 | US6261952 Method of forming copper interconnects with reduced in-line diffusion |
| 07/17/2001 | US6261951 Plasma treatment to enhance inorganic dielectric adhesion to copper |
| 07/17/2001 | US6261950 Self-aligned metal caps for interlevel metal connections |
| 07/17/2001 | US6261949 Method for manufacturing semiconductor device |
| 07/17/2001 | US6261947 Formation of electrical contacts to conductive elements in the fabrication of semiconductor integrated circuits |
| 07/17/2001 | US6261946 Method for forming semiconductor seed layers by high bias deposition |
| 07/17/2001 | US6261945 Crackstop and oxygen barrier for low-K dielectric integrated circuits |
| 07/17/2001 | US6261944 Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect |
| 07/17/2001 | US6261942 Dual metal-oxide layer as air bridge |
| 07/17/2001 | US6261940 Semiconductor method of making electrical connection between an electrically conductive line and a node location, and integrated circuitry |
| 07/17/2001 | US6261939 Pad metallization over active circuitry |
| 07/17/2001 | US6261938 Fabrication of sub-micron etch-resistant metal/semiconductor structures using resistless electron beam lithography |
| 07/17/2001 | US6261937 Method for forming a semiconductor fuse |
| 07/17/2001 | US6261936 Poly gate CD passivation for metrology control |
| 07/17/2001 | US6261935 Method of forming contact to polysilicon gate for MOS devices |
| 07/17/2001 | US6261934 Dry etch process for small-geometry metal gates over thin gate dielectric |
| 07/17/2001 | US6261933 Process for building borderless bitline, wordline amd DRAM structure |
| 07/17/2001 | US6261932 Method of fabricating Schottky diode and related structure |
| 07/17/2001 | US6261931 High quality, semi-insulating gallium nitride and method and system for forming same |
| 07/17/2001 | US6261930 Method for forming a hemispherical-grain polysilicon |
| 07/17/2001 | US6261929 Methods of forming a plurality of semiconductor layers using spaced trench arrays |
| 07/17/2001 | US6261928 Producing microstructures or nanostructures on a support |
| 07/17/2001 | US6261927 Method of forming defect-free ceramic structures using thermally depolymerizable surface layer |
| 07/17/2001 | US6261926 Method for fabricating field oxide |
| 07/17/2001 | US6261925 N2O Nitrided-oxide trench sidewalls to prevent boron outdiffusion and decrease stress |
| 07/17/2001 | US6261924 Maskless process for self-aligned contacts |
| 07/17/2001 | US6261923 Method to solve the dishing issue in CMP planarization by using a nitride hard mask for local inverse etchback and CMP |
| 07/17/2001 | US6261922 Methods of forming trench isolation regions |
| 07/17/2001 | US6261921 Method of forming shallow trench isolation structure |
| 07/17/2001 | US6261920 N-channel MOSFET having STI structure and method for manufacturing the same |
| 07/17/2001 | US6261919 Semiconductor device and method of manufacturing the same |
| 07/17/2001 | US6261917 High-K MOM capacitor |
| 07/17/2001 | US6261916 Process for fabricating integrated multi-crystal silicon resistors in MOS technology, and integrated MOS device comprising multi-crystal silicon resistors |
| 07/17/2001 | US6261915 Process of making polysilicon resistor |
| 07/17/2001 | US6261914 Process for improving local uniformity of chemical mechanical polishing using a self-aligned polish rate enhancement layer |
| 07/17/2001 | US6261913 Method for using thin spacers and oxidation in gate oxides |
| 07/17/2001 | US6261912 Method of fabricating a transistor |
| 07/17/2001 | US6261911 Method of manufacturing a junction in a semiconductor device |
| 07/17/2001 | US6261910 Semiconductor device and method of manufacturing the same |
| 07/17/2001 | US6261909 Semiconductor device having ultra shallow junctions and a reduced channel length and method for making same |
| 07/17/2001 | US6261908 Buried local interconnect |
| 07/17/2001 | US6261907 Method of forming a flash EEPROM device by employing polysilicon sidewall spacer as an erase gate |
| 07/17/2001 | US6261906 Method for forming a flash memory cell with improved drain erase performance |
| 07/17/2001 | US6261905 Flash memory structure with stacking gate formed using damascene-like structure |
| 07/17/2001 | US6261904 Dual bit isolation scheme for flash devices |
| 07/17/2001 | US6261903 Floating gate method and device |
| 07/17/2001 | US6261902 Method of forming a transistor structure |
| 07/17/2001 | US6261901 Method of manufacturing a DRAM capacitor with a dielectric column |
| 07/17/2001 | US6261900 Method for fabricating a DRAM capacitor |
| 07/17/2001 | US6261899 Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry |
| 07/17/2001 | US6261898 Method for fabricating a salicide gate |
| 07/17/2001 | US6261897 Method of manufacturing a semiconductor device |
| 07/17/2001 | US6261896 Memory device and method of forming the same |
| 07/17/2001 | US6261895 Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitor |
| 07/17/2001 | US6261894 Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays |
| 07/17/2001 | US6261893 Method for forming a magnetic layer of magnetic random access memory |
| 07/17/2001 | US6261892 Intra-chip AC isolation of RF passive components |
| 07/17/2001 | US6261891 Method of forming a passivation layer of a DRAM |
| 07/17/2001 | US6261890 Semiconductor device having capacitor and method of manufacturing the same |
| 07/17/2001 | US6261889 Manufacturing method of semiconductor device |
| 07/17/2001 | US6261888 Method of forming CMOS integrated circuitry |
| 07/17/2001 | US6261887 Transistors with independently formed gate structures and method |
| 07/17/2001 | US6261886 Increased gate to body coupling and application to DRAM and dynamic circuits |
| 07/17/2001 | US6261885 Method for forming integrated circuit gate conductors from dual layers of polysilicon |
| 07/17/2001 | US6261883 Semiconductor integrated circuit device, and fabrication process and designing method thereof |
| 07/17/2001 | US6261882 Method for fabricating a semiconductor device |
| 07/17/2001 | US6261881 Semiconductor device provided with semiconductor circuit consisting of semiconductor element and method of manufacturing the same |
| 07/17/2001 | US6261880 Process for manufacturing thin film transistors |
| 07/17/2001 | US6261877 Method of manufacturing gate insulated field effect transistors |
| 07/17/2001 | US6261876 Planar mixed SOI-bulk substrate for microelectronic applications |
| 07/17/2001 | US6261875 Transistor and process for fabricating the same |
| 07/17/2001 | US6261874 Fast recovery diode and method for its manufacture |
| 07/17/2001 | US6261871 Method and structure for temperature stabilization in flip chip technology |
| 07/17/2001 | US6261870 Backside failure analysis capable integrated circuit packaging |
| 07/17/2001 | US6261866 Method and apparatus for sealing a chip carrier and lid |
| 07/17/2001 | US6261865 Multi chip semiconductor package and method of construction |
| 07/17/2001 | US6261864 Low-pin-count chip package and manufacturing method thereof |
| 07/17/2001 | US6261860 Method of fabricating solid-state image sensor |
| 07/17/2001 | US6261859 Method for fabricating surface-emitting semiconductor device, surface-emitting semiconductor device fabricated by the method, and display device using the device |
| 07/17/2001 | US6261857 Process for fabricating an optical waveguide |
| 07/17/2001 | US6261856 Method and system of laser processing |
| 07/17/2001 | US6261855 Method for fabricating a semiconductor optical device |
| 07/17/2001 | US6261853 Method and apparatus for preparing semiconductor wafers for measurement |
| 07/17/2001 | US6261852 Check abnormal contact and via holes by electroplating method |
| 07/17/2001 | US6261851 Optimization of CMP process by detecting of oxide/nitride interface using IR system |
| 07/17/2001 | US6261850 Direct writing of low carbon conductive material |