| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 07/03/2001 | US6255726 Vertical interconnect process for silicon segments with dielectric isolation |
| 07/03/2001 | US6255721 Method and tool for handling micro-mechanical structures |
| 07/03/2001 | US6255718 Laser ablateable material |
| 07/03/2001 | US6255717 Shallow trench isolation using antireflection layer |
| 07/03/2001 | US6255716 Bipolar junction transistors having base electrode extensions |
| 07/03/2001 | US6255715 Fuse window guard ring structure for nitride capped self aligned contact processes |
| 07/03/2001 | US6255714 Integrated circuit having a micromagnetic device including a ferromagnetic core and method of manufacture therefor |
| 07/03/2001 | US6255712 Semi-sacrificial diamond for air dielectric formation |
| 07/03/2001 | US6255711 Encroachless LOCOS isolation |
| 07/03/2001 | US6255710 3-D smart power IC |
| 07/03/2001 | US6255706 Thin film transistor and method of manufacturing same |
| 07/03/2001 | US6255705 Producing devices having both active matrix display circuits and peripheral circuits on a same substrate |
| 07/03/2001 | US6255704 Semiconductor device and method for fabricating the same |
| 07/03/2001 | US6255703 Device with lower LDD resistance |
| 07/03/2001 | US6255702 Semiconductor device having junction depths for reducing short channel effect |
| 07/03/2001 | US6255701 Semiconductor device containing local interconnection and method of manufacturing the same |
| 07/03/2001 | US6255700 CMOS semiconductor device |
| 07/03/2001 | US6255699 Pillar CMOS structure |
| 07/03/2001 | US6255698 Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit |
| 07/03/2001 | US6255697 Integrated circuit devices including distributed and isolated dummy conductive regions |
| 07/03/2001 | US6255696 Retrograde ESD protection apparatus |
| 07/03/2001 | US6255695 TFT CMOS logic circuit having source/drain electrodes of differing spacing from the gate electrode for decreasing wiring capacitance and power consumption |
| 07/03/2001 | US6255694 Multi-function semiconductor structure and method |
| 07/03/2001 | US6255693 Ion implantation with programmable energy, angle, and beam current |
| 07/03/2001 | US6255692 Trench-gate semiconductor device |
| 07/03/2001 | US6255691 Nonvolatile semiconductor memory device and manufacturing process thereof |
| 07/03/2001 | US6255690 Non-volatile semiconductor memory device |
| 07/03/2001 | US6255689 Flash memory structure and method of manufacture |
| 07/03/2001 | US6255688 A capacitor dielectric that is subject to reduction by titanium and sandwiched between one electrode located on an interconnect made of layers of aluminum or aluminum alloy and a second electrode |
| 07/03/2001 | US6255687 Doped silicon structure with impression image on opposing roughened surfaces |
| 07/03/2001 | US6255686 Semiconductor storage device including short circuit avoiding structure and method of fabricating thereof |
| 07/03/2001 | US6255685 Semiconductor device and method of manufacturing the same |
| 07/03/2001 | US6255684 DRAM cell configuration and method for its production |
| 07/03/2001 | US6255683 Dynamic random access memory |
| 07/03/2001 | US6255682 Trench DRAM cells with self-aligned field plate |
| 07/03/2001 | US6255679 Field effect transistor which can operate stably in millimeter wave band |
| 07/03/2001 | US6255678 Apparatus for measuring physical and chemical phenomena |
| 07/03/2001 | US6255675 Programmable capacitor for an integrated circuit |
| 07/03/2001 | US6255673 Hetero-junction field effect transistor |
| 07/03/2001 | US6255671 Metal embedded passivation layer structure for microelectronic interconnect formation, customization and repair |
| 07/03/2001 | US6255668 Thin film transistor with inclined eletrode side surfaces |
| 07/03/2001 | US6255663 Charged particle beam exposure apparatus and semiconductor device manufacturing method |
| 07/03/2001 | US6255661 Mirror projection system for a scanning lithographic projection apparatus, and lithographic apparatus comprising such a system |
| 07/03/2001 | US6255601 Conductive feedthrough for a ceramic body and method of fabricating same |
| 07/03/2001 | US6255599 Relocating the neutral plane in a PBGA substrate to eliminate chip crack and interfacial delamination |
| 07/03/2001 | US6255586 Interlocked bonding pad structures and methods of fabrication therefor |
| 07/03/2001 | US6255585 Packaging and interconnection of contact structure |
| 07/03/2001 | US6255447 Oligomers or polymers which demonstrate fluorescence, high glass transition temperatures or liquid-crystalline properties; facilitate preparation of films having high heat resistance and solvent resistance |
| 07/03/2001 | US6255423 Pressure sensitive adhesive sheet and use thereof |
| 07/03/2001 | US6255405 Radiation absorbing copolymer comprising recurring unit containing organic chromophore |
| 07/03/2001 | US6255233 In-situ silicon nitride and silicon based oxide deposition with graded interface for damascene application |
| 07/03/2001 | US6255232 Spin-on-polymer dielectric material being susceptible to greater shrinkage when thermally processed at sub-atmospheric pressure than when thermally processed at atmospheric pressure; polyarylene ether or fluorinated polyarylene ether |
| 07/03/2001 | US6255231 Method for forming a gate oxide layer |
| 07/03/2001 | US6255230 Method for modifying a film forming surface of a substrate on which a film is to be formed, and method for manufacturing a semiconductor device using the same |
| 07/03/2001 | US6255229 Method for forming semiconductor dielectric layer |
| 07/03/2001 | US6255228 Method for removing contaminants from a semiconductor wafer |
| 07/03/2001 | US6255227 Etching process of CoSi2 layers |
| 07/03/2001 | US6255226 Optimized metal etch process to enable the use of aluminum plugs |
| 07/03/2001 | US6255225 Method of forming a resist pattern, a method of manufacturing semiconductor device by the same method, and a device and a hot plate for forming a resist pattern |
| 07/03/2001 | US6255224 Method of forming contact for semiconductor device |
| 07/03/2001 | US6255223 Substrate handling method and apparatus, and attractive force inspection method and apparatus used therewith |
| 07/03/2001 | US6255222 Method for removing residue from substrate processing chamber exhaust line for silicon-oxygen-carbon deposition process |
| 07/03/2001 | US6255221 Methods for running a high density plasma etcher to achieve reduced transistor device damage |
| 07/03/2001 | US6255219 Method for fabricating high-performance submicron MOSFET with lateral asymmetric channel |
| 07/03/2001 | US6255218 Semiconductor device and fabrication method thereof |
| 07/03/2001 | US6255217 Plasma treatment to enhance inorganic dielectric adhesion to copper |
| 07/03/2001 | US6255216 Forming titanium silicide by chemical vapor deposition (cvd) on an exposed silicon base layer of the contact hole; forming a barrier layer on the titanium silicide; and forming a plug material on the barrier layer. |
| 07/03/2001 | US6255215 Semiconductor device having silicide layers formed using a collimated metal layer |
| 07/03/2001 | US6255214 Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions |
| 07/03/2001 | US6255213 Method of forming a structure upon a semiconductive substrate |
| 07/03/2001 | US6255211 Silicon carbide stop layer in chemical mechanical polishing over metallization layers |
| 07/03/2001 | US6255210 Semiconductor dielectric structure and method for making the same |
| 07/03/2001 | US6255209 Methods of forming a contact having titanium formed by chemical vapor deposition |
| 07/03/2001 | US6255208 Selective wafer-level testing and burn-in |
| 07/03/2001 | US6255207 Composite planarizing dielectric layer employing high density plasma chemical vapor deposited (HDP-CVD) underlayer |
| 07/03/2001 | US6255206 Method of forming gate electrode with titanium polycide structure |
| 07/03/2001 | US6255205 High density programmable read-only memory employing double-wall spacers |
| 07/03/2001 | US6255204 Method for forming a semiconductor device |
| 07/03/2001 | US6255203 Technique for low-temperature formation of excellent silicided α-Si gate structures |
| 07/03/2001 | US6255202 Damascene T-gate using a spacer flow |
| 07/03/2001 | US6255201 Method and device for activating semiconductor impurities |
| 07/03/2001 | US6255200 Polysilicon structure and process for improving CMOS device performance |
| 07/03/2001 | US6255199 Method of producing polycrystalline silicon |
| 07/03/2001 | US6255198 Methods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed thereby |
| 07/03/2001 | US6255197 Hydrogen annealing method and apparatus |
| 07/03/2001 | US6255196 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions |
| 07/03/2001 | US6255195 Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method |
| 07/03/2001 | US6255194 Trench isolation method |
| 07/03/2001 | US6255193 Method for fabricating an isolation trench using an auxiliary layer |
| 07/03/2001 | US6255192 Methods for barrier layer formation |
| 07/03/2001 | US6255191 Method of fabricating an isolation structure in an integrated circuit |
| 07/03/2001 | US6255190 Method for dielectrically isolated deep pn-junctions in silicon substrates using deep trench sidewall predeposition technology |
| 07/03/2001 | US6255189 Method of manufacturing a semiconductor device in a silicon body, a surface of said silicon body being provided with an alignment grating and an at least partly recessed oxide pattern |
| 07/03/2001 | US6255188 Method of removing a polysilicon buffer using an etching selectivity solution |
| 07/03/2001 | US6255187 Method of fabricating self-aligning stacked capacitor using electroplating method |
| 07/03/2001 | US6255186 Methods of forming integrated circuitry and capacitors having a capacitor electrode having a base and a pair of walls projecting upwardly therefrom |
| 07/03/2001 | US6255185 Two step anneal for controlling resistor tolerance |
| 07/03/2001 | US6255184 Fabrication process for a three dimensional trench emitter bipolar transistor |
| 07/03/2001 | US6255183 Manufacture of a semiconductor device with a MOS transistor having an LDD structure using SiGe spacers |
| 07/03/2001 | US6255182 Method of forming a gate structure of a transistor by means of scalable spacer technology |