| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 07/10/2001 | US6259163 Bond pad for stress releif between a substrate and an external substrate |
| 07/10/2001 | US6259162 Method for reducing capactive coupling between conductive lines |
| 07/10/2001 | US6259160 Apparatus and method of encapsulated copper (Cu) Interconnect formation |
| 07/10/2001 | US6259159 Reflowed solder ball with low melting point metal cap |
| 07/10/2001 | US6259158 Semiconductor device utilizing an external electrode with a small pitch connected to a substrate |
| 07/10/2001 | US6259156 Semiconductor device and method for manufacturing same |
| 07/10/2001 | US6259154 Semiconductor device and method of manufacturing the same |
| 07/10/2001 | US6259151 Use of barrier refractive or anti-reflective layer to improve laser trim characteristics of thin film resistors |
| 07/10/2001 | US6259150 Voltage dividing resistor and voltage dividing circuit |
| 07/10/2001 | US6259149 Fully isolated thin-film trench capacitor |
| 07/10/2001 | US6259148 Modular high frequency integrated circuit structure |
| 07/10/2001 | US6259147 Semiconductor device having a fuse layer |
| 07/10/2001 | US6259145 Reduced leakage trench isolation |
| 07/10/2001 | US6259144 Electronic memory structure |
| 07/10/2001 | US6259143 Semiconductor memory device of NOR type mask ROM and manufacturing method of the same |
| 07/10/2001 | US6259142 Multiple split gate semiconductor device and fabrication method |
| 07/10/2001 | US6259141 Insulated gate field effect semiconductor device and forming method thereof |
| 07/10/2001 | US6259138 Semiconductor device having multilayered gate electrode and impurity regions overlapping therewith |
| 07/10/2001 | US6259137 Defect induced buried oxide (DIBOX) for throughput SOI |
| 07/10/2001 | US6259135 MOS transistors structure for reducing the size of pitch limited circuits |
| 07/10/2001 | US6259133 Method for forming an integrated circuit memory cell and product thereof |
| 07/10/2001 | US6259132 Array of electrically programmable non-volatile semiconductor memory cells comprising ROM memory cells |
| 07/10/2001 | US6259131 Poly tip and self aligned source for split-gate flash cell |
| 07/10/2001 | US6259130 High density flash memories with high capacitive-couping ratio and high speed operation |
| 07/10/2001 | US6259129 Strap with intrinsically conductive barrier |
| 07/10/2001 | US6259128 Metal-insulator-metal capacitor for copper damascene process and method of forming the same |
| 07/10/2001 | US6259127 Integrated circuit container having partially rugged surface |
| 07/10/2001 | US6259126 Low cost mixed memory integration with FERAM |
| 07/10/2001 | US6259125 Scalable high dielectric constant capacitor |
| 07/10/2001 | US6259122 Group III nitride semiconductor light-emitting device having anticracking feature |
| 07/10/2001 | US6259120 Semiconductor device and method for fabricating the same |
| 07/10/2001 | US6259119 Liquid crystal display and method of manufacturing the same |
| 07/10/2001 | US6259118 Ultra high density NOR gate using a stacked transistor arrangement |
| 07/10/2001 | US6259115 Dummy patterning for semiconductor manufacturing processes |
| 07/10/2001 | US6259106 Apparatus and method for controlling a beam shape |
| 07/10/2001 | US6259105 System and method for cleaning silicon-coated surfaces in an ion implanter |
| 07/10/2001 | US6259094 Electron beam inspection method and apparatus |
| 07/10/2001 | US6259072 Zone controlled radiant heating system utilizing focused reflector |
| 07/10/2001 | US6259066 Process and device for processing a material by electromagnetic radiation in a controlled atmosphere |
| 07/10/2001 | US6259062 Process chamber cooling |
| 07/10/2001 | US6259061 Vertical-heat-treatment apparatus with movable lid and compensation heater movable therewith |
| 07/10/2001 | US6259058 Apparatus for separating non-metallic substrates |
| 07/10/2001 | US6259038 Semiconductor chip mounting board and method of inspecting the same mounting board |
| 07/10/2001 | US6259037 Polytetrafluoroethylene thin film chip carrier |
| 07/10/2001 | US6259036 Method for fabricating electronic assemblies using semi-cured conductive elastomeric bumps |
| 07/10/2001 | US6258735 Method for using bypass lines to stabilize gas flow and maintain plasma inside a deposition chamber |
| 07/10/2001 | US6258734 Method for patterning semiconductor devices on a silicon substrate using oxynitride film |
| 07/10/2001 | US6258733 Method and apparatus for misted liquid source deposition of thin film with reduced mist particle size |
| 07/10/2001 | US6258732 Method of forming a patterned organic dielectric layer on a substrate |
| 07/10/2001 | US6258731 Method for fabricating oxide film |
| 07/10/2001 | US6258730 Ultra-thin gate oxide formation using an N2O plasma |
| 07/10/2001 | US6258729 Oxide etching method and structures resulting from same |
| 07/10/2001 | US6258728 Plasma etching methods |
| 07/10/2001 | US6258727 Method of forming metal lands at the M0 level with a non selective chemistry |
| 07/10/2001 | US6258726 Method of forming isolation film for semiconductor devices |
| 07/10/2001 | US6258725 Method for forming metal line of semiconductor device by (TiA1)N anti-reflective coating layer |
| 07/10/2001 | US6258724 Low dielectric constant dielectric films and process for making the same |
| 07/10/2001 | US6258723 Dry etching method and a TFT fabrication method |
| 07/10/2001 | US6258722 Method of manufacturing CMOS device |
| 07/10/2001 | US6258721 Diamond slurry for chemical-mechanical planarization of semiconductor wafers |
| 07/10/2001 | US6258720 Method of formation of conductive lines on integrated circuits |
| 07/10/2001 | US6258719 Intermetallic aluminides and silicides articles, such as sputtering targets, and methods of making same |
| 07/10/2001 | US6258718 Method for reducing surface charge on semiconductor wafers to prevent arcing during plasma deposition |
| 07/10/2001 | US6258717 Method to produce high quality metal fill in deep submicron vias and lines |
| 07/10/2001 | US6258716 CVD titanium silicide for contact hole plugs |
| 07/10/2001 | US6258715 Process for low-k dielectric with dummy plugs |
| 07/10/2001 | US6258714 Self-aligned contacts for salicided MOS devices |
| 07/10/2001 | US6258713 Method for forming dual damascene structure |
| 07/10/2001 | US6258712 Method for forming a borderless contact |
| 07/10/2001 | US6258711 Sacrificial deposit to improve damascene pattern planarization in semiconductor wafers |
| 07/10/2001 | US6258710 Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity |
| 07/10/2001 | US6258709 Formation of electrical interconnect lines by selective metal etch |
| 07/10/2001 | US6258708 Method of fabricating gate contact pods, load lines and wiring structures using a minimum number of etching steps |
| 07/10/2001 | US6258707 Triple damascence tungsten-copper interconnect structure |
| 07/10/2001 | US6258705 Method of forming circuit probing contact points on fine pitch peripheral bond pads on flip chip |
| 07/10/2001 | US6258704 Methods for fabricating dimpled contacts for metal-to-semiconductor connections |
| 07/10/2001 | US6258703 Reflow of low melt solder tip C4's |
| 07/10/2001 | US6258702 Method for the formation of a cuprous oxide film and process for the production of a semiconductor device using said method |
| 07/10/2001 | US6258701 Process for forming insulating structures for integrated circuits |
| 07/10/2001 | US6258700 Silicide agglomeration fuse device |
| 07/10/2001 | US6258698 Process for producing semiconductor substrate |
| 07/10/2001 | US6258697 Method of etching contacts with reduced oxide stress |
| 07/10/2001 | US6258696 System and method for fabricating semiconductor device and isolation structure thereof |
| 07/10/2001 | US6258695 Dislocation suppression by carbon incorporation |
| 07/10/2001 | US6258694 Fabrication method of a device isolation structure |
| 07/10/2001 | US6258693 Ion implantation for scalability of isolation in an integrated circuit |
| 07/10/2001 | US6258692 Method forming shallow trench isolation |
| 07/10/2001 | US6258691 Cylindrical capacitor and method for fabricating same |
| 07/10/2001 | US6258690 Method of manufacturing semiconductor device |
| 07/10/2001 | US6258689 Low resistance fill for deep trench capacitor |
| 07/10/2001 | US6258688 Method to form a high Q inductor |
| 07/10/2001 | US6258686 Manufacturing method of semiconductor device and semiconductor device |
| 07/10/2001 | US6258685 Method of manufacturing hetero-junction bipolar transistor |
| 07/10/2001 | US6258684 Method of fabricating semiconductor memory device having a soi structure |
| 07/10/2001 | US6258683 Local interconnection arrangement with reduced junction leakage and method of forming same |
| 07/10/2001 | US6258682 Method of making ultra shallow junction MOSFET |
| 07/10/2001 | US6258681 Use of a rapid thermal anneal process to control drive current |
| 07/10/2001 | US6258680 Integrated circuit gate conductor which uses layered spacers to produce a graded junction |
| 07/10/2001 | US6258679 Sacrificial silicon sidewall for damascene gate formation |
| 07/10/2001 | US6258678 Use of a wet etch dip step used as part of a self-aligned contact opening procedure |