Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2001
07/31/2001US6269047 Semiconductor memory device
07/31/2001US6269027 Non-volatile storage latch
07/31/2001US6268994 Electrostatic chuck and method of manufacture
07/31/2001US6268990 Semiconductor protection device and power converting system
07/31/2001US6268916 System for non-destructive measurement of samples
07/31/2001US6268907 Elimination of standing waves in photoresist
07/31/2001US6268906 Exposure apparatus and exposure method
07/31/2001US6268903 Method of adjusting projection optical apparatus
07/31/2001US6268902 Exposure apparatus, and manufacturing method for devices using same
07/31/2001US6268900 Accommodating apparatus and substrate processing system
07/31/2001US6268842 Thin film transistor circuit and semiconductor display device using the same
07/31/2001US6268779 Integrated oscillators and tuning circuits
07/31/2001US6268764 Bandgap voltage comparator used as a low voltage detection circuit
07/31/2001US6268761 Booster circuit
07/31/2001US6268760 Hysteretic fuse control circuit with serial interface fusing
07/31/2001US6268757 Semiconductor device having capacitor that reduce fluctuation of power supply
07/31/2001US6268740 System for testing semiconductor device formed on semiconductor wafer
07/31/2001US6268718 Burn-in test device
07/31/2001US6268700 Vacuum plasma processor having coil with intermediate portion coupling lower magnetic flux density to plasma than center and peripheral portions of the coil
07/31/2001US6268662 Wire bonded flip-chip assembly of semiconductor devices
07/31/2001US6268661 Semiconductor device and method of its fabrication
07/31/2001US6268659 Semiconductor body with layer of solder material comprising chromium
07/31/2001US6268658 Semiconductor integrated circuit device for connecting semiconductor region and electrical wiring metal via titanium silicide layer and method of fabrication thereof
07/31/2001US6268657 Semiconductor devices and an insulating layer with an impurity
07/31/2001US6268656 Method and structure for uniform height solder bumps on a semiconductor wafer
07/31/2001US6268655 Semiconductor device including edge bond pads and methods
07/31/2001US6268652 CSP type semiconductor device with reduced package size
07/31/2001US6268648 Board for mounting semiconductor element, method for manufacturing the same, and semiconductor device
07/31/2001US6268647 Electronic component with an insulating coating
07/31/2001US6268645 Semiconductor device
07/31/2001US6268644 Semiconductor device
07/31/2001US6268643 Lead frame device for delivering electrical power to a semiconductor die
07/31/2001US6268641 Semiconductor wafer having identification indication and method of manufacturing the same
07/31/2001US6268640 Forming steep lateral doping distribution at source/drain junctions
07/31/2001US6268638 Metal wire fuse structure with cavity
07/31/2001US6268637 Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication
07/31/2001US6268636 Operation and biasing for single device equivalent to CMOS
07/31/2001US6268634 Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant
07/31/2001US6268633 Electronic structure comprising high and low voltage transistors, and a corresponding fabrication method
07/31/2001US6268632 Field effect transistor and power amplifier including the same
07/31/2001US6268631 Glass substrate assembly, semiconductor device and method of heat-treating glass substrate
07/31/2001US6268630 Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications
07/31/2001US6268629 Field effect transistor with reduced narrow channel effect
07/31/2001US6268628 Depletion type MOS semiconductor device and MOS power IC
07/31/2001US6268627 Semiconductor device having impurity regions with varying impurity concentrations
07/31/2001US6268626 DMOS field effect transistor with improved electrical characteristics and method for manufacturing the same
07/31/2001US6268625 Trench-type thin film transistor
07/31/2001US6268624 Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing
07/31/2001US6268623 Apparatus and method for margin testing single polysilicon EEPROM cells
07/31/2001US6268622 Non-volatile memory device and fabrication method thereof
07/31/2001US6268621 Vertical channel field effect transistor
07/31/2001US6268620 Method of forming capacitors on integrated circuit
07/31/2001US6268619 Integrated circuits
07/31/2001US6268608 Method and apparatus for selective in-situ etching of inter dielectric layers
07/31/2001US6268606 Electrostatic deflector, for electron beam exposure apparatus, with reduced charge-up
07/31/2001US6268457 Spin-on glass anti-reflective coatings for photolithography
07/31/2001US6268323 Mixture of solvent, alkanolamine and corrosion resistance
07/31/2001US6268299 Variable stoichiometry silicon nitride barrier films for tunable etch selectivity and enhanced hyrogen permeability
07/31/2001US6268298 Method of manufacturing semiconductor device
07/31/2001US6268297 Self-planarizing low-temperature doped-silicate-glass process capable of gap-filling narrow spaces
07/31/2001US6268296 Low temperature process for multiple voltage devices
07/31/2001US6268295 Method of manufacturing semiconductor device
07/31/2001US6268294 Attenuated degradation of a polyarylene ether dielectric
07/31/2001US6268293 Method of forming wires on an integrated circuit chip
07/31/2001US6268292 Methods for use in formation of titanium nitride interconnects
07/31/2001US6268291 Method for forming electromigration-resistant structures by doping
07/31/2001US6268290 Method of forming wirings
07/31/2001US6268289 Method for protecting the edge exclusion of a semiconductor wafer from copper plating through use of an edge exclusion masking layer
07/31/2001US6268288 Plasma treated thermal CVD of TaN films from tantalum halide precursors
07/31/2001US6268287 Polymerless metal hard mask etching
07/31/2001US6268286 Method of fabricating MOSFET with lateral resistor with ballasting
07/31/2001US6268285 Method of removing plasma etch damage to pre-silicidized surfaces by wet silicon etch
07/31/2001US6268284 In situ titanium aluminide deposit in high aspect ratio features
07/31/2001US6268283 Method for forming dual damascene structure
07/31/2001US6268282 Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks
07/31/2001US6268281 Method to form self-aligned contacts with polysilicon plugs
07/31/2001US6268280 Semiconductor device using dual damascene technology and method for manufacturing the same
07/31/2001US6268279 Trench and via formation in insulating films utilizing a patterned etching stopper film
07/31/2001US6268278 Semiconductor device and manufacturing process thereof
07/31/2001US6268277 Method of producing air gap for reducing intralayer capacitance in metal layers in damascene metalization process and product resulting therefrom
07/31/2001US6268276 Area array air gap structure for intermetal dielectric application
07/31/2001US6268275 Method of locating conductive spheres utilizing screen and hopper of solder balls
07/31/2001US6268274 Low temperature process for forming inter-metal gap-filling insulating layers in silicon wafer integrated circuitry
07/31/2001US6268273 Fabrication method of single electron tunneling device
07/31/2001US6268272 Method of forming gate electrode with titanium polycide
07/31/2001US6268271 Method for forming buried layer inside a semiconductor device
07/31/2001US6268269 Method for fabricating an oxide layer on silicon with carbon ions introduced at the silicon/oxide interface in order to reduce hot carrier effects
07/31/2001US6268268 Method of manufacturing semiconductor device
07/31/2001US6268267 Vapor deposition
07/31/2001US6268266 Method for forming enhanced FOX region of low voltage device in high voltage process
07/31/2001US6268265 Trench isolation method for semiconductor integrated circuit
07/31/2001US6268264 Method of forming shallow trench isolation
07/31/2001US6268263 Method of forming a trench type element isolation in semiconductor substrate
07/31/2001US6268262 Method for forming air bridges
07/31/2001US6268261 Microprocessor having air as a dielectric and encapsulated lines and process for manufacture
07/31/2001US6268260 Methods of forming memory cell capacitor plates in memory cell capacitor structures
07/31/2001US6268259 Overhanging separator for self-defining stacked capacitor
07/31/2001US6268258 Method for fabricating capacitor in semiconductor device
07/31/2001US6268257 Method of forming a transistor having a low-resistance gate electrode
07/31/2001US6268256 Method for reducing short channel effect