Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2001
08/07/2001US6271135 Patterning photoresist; filling with copper; removal photoresist; encapsulation; prevention copper diffusion
08/07/2001US6271134 Apparatus for manufacturing semiconductor device method for forming HSG-polysilicon layer using same and method for forming capacitor having electrode of HSG-polysilicon layer
08/07/2001US6271133 Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication
08/07/2001US6271132 Self-aligned source and drain extensions fabricated in a damascene contact and gate process
08/07/2001US6271131 Methods for forming rhodium-containing layers such as platinum-rhodium barrier layers
08/07/2001US6271130 Semiconductor assisted metal deposition for nanolithography applications
08/07/2001US6271129 Method for forming a gap filling refractory metal layer having reduced stress
08/07/2001US6271128 Method for fabricating transistor
08/07/2001US6271127 Method for dual damascene process using electron beam and ion implantation cure methods for low dielectric constant materials
08/07/2001US6271125 Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure
08/07/2001US6271124 Method of making a dynamic random access memory device utilizing chemical mechanical polishing
08/07/2001US6271123 Chemical-mechanical polish method using an undoped silicon glass stop layer for polishing BPSG
08/07/2001US6271122 Method of compensating for material loss in a metal silicone layer in contacts of integrated circuit devices
08/07/2001US6271121 Applying hydrogen plasma; then hydrogen and tungsten fluoride
08/07/2001US6271120 Forming titanium nitride barrier by rapid thermal annealing of titanium silicide
08/07/2001US6271119 Method for making semiconductor device
08/07/2001US6271118 Method of applying partial reverse mask
08/07/2001US6271117 Process for a nail shaped landing pad plug
08/07/2001US6271116 Method of fabricating interconnects
08/07/2001US6271115 Post metal etch photoresist strip method
08/07/2001US6271114 System for adjusting the size of conductive lines based upon the contact size
08/07/2001US6271113 Method for forming wiring in semiconductor device
08/07/2001US6271112 Interlayer between titanium nitride and high density plasma oxide
08/07/2001US6271111 High density pluggable connector array and process thereof
08/07/2001US6271110 Bump-forming method using two plates and electronic device
08/07/2001US6271109 Substrate for accommodating warped semiconductor devices
08/07/2001US6271108 Method of forming a contact in semiconductor device
08/07/2001US6271107 Semiconductor with polymeric layer
08/07/2001US6271106 Method of manufacturing a semiconductor component
08/07/2001US6271105 Method of forming multiple wells in a semiconductor integrated circuit using fewer photolithography steps
08/07/2001US6271104 Semiconductor wafer; etching pattern in barrier layer
08/07/2001US6271103 Solid state image sensor and method for fabricating the same
08/07/2001US6271102 Method and system for dicing wafers, and semiconductor structures incorporating the products thereof
08/07/2001US6271101 Process for production of SOI substrate and process for production of semiconductor device
08/07/2001US6271100 Chemically enhanced anneal for removing trench stress resulting in improved bipolar yield
08/07/2001US6271099 Method for forming a capacitor of a DRAM cell
08/07/2001US6271098 Multilayer intermetallic
08/07/2001US6271097 Method of fabricating a low base-resistance bipolar transistor
08/07/2001US6271096 Method and device for improved salicide resistance on polysilicon gates
08/07/2001US6271095 Locally confined deep pocket process for ULSI mosfets
08/07/2001US6271094 Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
08/07/2001US6271093 Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETs
08/07/2001US6271092 Method for fabricating a semiconductor device
08/07/2001US6271091 Method of fabricating flash memory cell
08/07/2001US6271090 Method for manufacturing flash memory device with dual floating gates and two bits per cell
08/07/2001US6271089 Method of manufacturing flash memory
08/07/2001US6271088 Method for fabricating a buried vertical split gate memory device with high coupling ratio
08/07/2001US6271087 Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects
08/07/2001US6271086 Method for preventing the cluster defect of HSG
08/07/2001US6271085 Method for forming a bottom electrode of a storage capacitor
08/07/2001US6271084 Method of fabricating a metal-insulator-metal (MIM), capacitor structure using a damascene process
08/07/2001US6271083 Method of forming a dram crown capacitor
08/07/2001US6271082 Method of fabricating a mixed circuit capacitor
08/07/2001US6271081 Semiconductor memory device
08/07/2001US6271080 Structure and method for planar MOSFET DRAM cell free of wordline gate conductor to storage trench overlay sensitivity
08/07/2001US6271079 Method of forming a trench capacitor
08/07/2001US6271078 Simplifying conductive plate/via isolation
08/07/2001US6271077 Thin film deposition method, capacitor device and method for fabricating the same, and semiconductor device and method for fabricating the same
08/07/2001US6271076 Method for fabricating a novel metallized oxide structure
08/07/2001US6271075 Method of manufacturing semiconductor device which can reduce manufacturing cost without dropping performance of logic mixed DRAM
08/07/2001US6271074 Process for producing an integrated semiconductor circuit
08/07/2001US6271073 Method of forming transistors in a peripheral circuit of a semiconductor memory device
08/07/2001US6271072 Method of manufacturing a storage node having five polysilicon bars
08/07/2001US6271071 Fabrication process for reduced area storage node junction
08/07/2001US6271070 Method of manufacturing semiconductor device
08/07/2001US6271069 Transistor
08/07/2001US6271068 Method for making improved polysilicon emitters for bipolar transistors on BiCMOS integrated circuits
08/07/2001US6271066 Semiconductor material and method for forming the same and thin film transistor
08/07/2001US6271065 Method directed to the manufacture of an SOI device
08/07/2001US6271064 Thin film transistor and method of manufacturing the same
08/07/2001US6271063 Method of making an SRAM cell and structure
08/07/2001US6271062 Thin film semiconductor device including a semiconductor film with high field-effect mobility
08/07/2001US6271061 Fabrication of insulated gate bipolar devices
08/07/2001US6271060 Process of fabricating a chip scale surface mount package for semiconductor device
08/07/2001US6271059 Chip interconnection structure using stub terminals
08/07/2001US6271058 Method of manufacturing semiconductor device in which semiconductor chip is mounted facedown on board
08/07/2001US6271057 Method of making semiconductor chip package
08/07/2001US6271050 Method of manufacturing thin film diode
08/07/2001US6271048 Process for recycling a substrate from an integrated circuit package
08/07/2001US6271047 Layer-thickness detection methods and apparatus for wafers and the like, and polishing apparatus comprising same
08/07/2001US6270948 Method of forming pattern
08/07/2001US6270947 Printing a pattern
08/07/2001US6270944 Thermal transfer element for forming multilayers devices
08/07/2001US6270942 Photosensitve polymer containing norbornene units, maleic anhydride units and unsaturated ester
08/07/2001US6270939 Radiation-sensitive resin composition
08/07/2001US6270929 Damascene T-gate using a relacs flow
08/07/2001US6270898 Tool tip and bonding tool comprising the tool tip and control method for the bonding tool
08/07/2001US6270879 Release member for use in producing a multi-layer printed wiring board
08/07/2001US6270862 Placing substrate on substrate holder in processing chamber, wherein an interior surface of a dielectric member forming a wall of process chamber faces substrate holder; supplying process gas into chamber; energizing to deposit film
08/07/2001US6270859 Plasma treatment of titanium nitride formed by chemical vapor deposition
08/07/2001US6270857 Method of modifying a surface of an insulator
08/07/2001US6270839 Device for feeding raw material for chemical vapor phase deposition and method therefor
08/07/2001US6270712 Molding die and marking method for semiconductor devices
08/07/2001US6270687 RF plasma method
08/07/2001US6270685 Method for producing a semiconductor
08/07/2001US6270647 Electroplating system having auxiliary electrode exterior to main reactor chamber for contact cleaning operations
08/07/2001US6270634 Method for plasma etching at a high etch rate
08/07/2001US6270622 Method and apparatus for improving accuracy of plasma etching process
08/07/2001US6270621 Etch chamber
08/07/2001US6270619 Treatment device, laser annealing device, manufacturing apparatus, and manufacturing apparatus for flat display device