| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 08/14/2001 | US6274854 Method and apparatus for baking out a gate valve in a semiconductor processing system |
| 08/14/2001 | US6274823 Interconnection substrates with resilient contact structures on both sides |
| 08/14/2001 | US6274822 Manufacture of semiconductor connection components with frangible lead sections |
| 08/14/2001 | US6274518 Method for producing a group III nitride compound semiconductor substrate |
| 08/14/2001 | US6274517 Method of fabricating an improved spacer |
| 08/14/2001 | US6274516 Radiating with ultraviolet light; generating ozone from oxygen |
| 08/14/2001 | US6274515 Spin-on dielectric formation process for use in manufacturing semiconductors |
| 08/14/2001 | US6274514 HDP-CVD method for forming passivation layers with enhanced adhesion |
| 08/14/2001 | US6274513 Method of oxidizing a nitride film on a conductive substrate |
| 08/14/2001 | US6274512 Method for manufacturing a semiconductor device |
| 08/14/2001 | US6274511 Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer |
| 08/14/2001 | US6274510 Lower temperature method for forming high quality silicon-nitrogen dielectrics |
| 08/14/2001 | US6274509 Global planarization method for inter-layer-dielectric and inter-metal dielectric |
| 08/14/2001 | US6274508 Apparatuses and methods used in forming assemblies |
| 08/14/2001 | US6274507 Plasma processing apparatus and method |
| 08/14/2001 | US6274506 Apparatus and method for dispensing processing fluid toward a substrate surface |
| 08/14/2001 | US6274505 Etching method, etching apparatus and analyzing method |
| 08/14/2001 | US6274504 Minimizing metal corrosion during post metal solvent clean |
| 08/14/2001 | US6274503 Etching method for doped polysilicon layer |
| 08/14/2001 | US6274502 Method for plasma etching |
| 08/14/2001 | US6274500 Single wafer in-situ dry clean and seasoning for plasma etching process |
| 08/14/2001 | US6274499 Method to avoid copper contamination during copper etching and CMP |
| 08/14/2001 | US6274498 Methods of forming materials within openings, and method of forming isolation regions |
| 08/14/2001 | US6274497 Copper damascene manufacturing process |
| 08/14/2001 | US6274496 Method for single chamber processing of PECVD-Ti and CVD-TiN films for integrated contact/barrier applications in IC manufacturing |
| 08/14/2001 | US6274494 Method of protecting gate oxide |
| 08/14/2001 | US6274493 Method for forming a via |
| 08/14/2001 | US6274492 Process and device for production of metallic coatings on semiconductor structures |
| 08/14/2001 | US6274491 Process of manufacturing thin ball grid array substrates |
| 08/14/2001 | US6274490 Method of manufacturing semiconductor devices having high pressure anneal |
| 08/14/2001 | US6274489 Manufacturing method of semiconductor apparatus |
| 08/14/2001 | US6274488 Method of forming a silicide region in a Si substrate and a device having same |
| 08/14/2001 | US6274487 Method for manufacturing semiconductor device |
| 08/14/2001 | US6274486 Metal contact and process |
| 08/14/2001 | US6274485 Method to reduce dishing in metal chemical-mechanical polishing |
| 08/14/2001 | US6274484 Fabrication process for low resistivity tungsten layer with good adhesion to insulator layers |
| 08/14/2001 | US6274483 Method to improve metal line adhesion by trench corner shape modification |
| 08/14/2001 | US6274482 Semiconductor processing methods of forming a contact opening |
| 08/14/2001 | US6274481 Process sequence to improve DRAM data retention |
| 08/14/2001 | US6274480 Method of Fabricating semiconductor device |
| 08/14/2001 | US6274479 Flowable germanium doped silicate glass for use as a spacer oxide |
| 08/14/2001 | US6274478 Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process |
| 08/14/2001 | US6274477 Method of fabricating conductive line structure |
| 08/14/2001 | US6274476 Semiconductor device and method of manufacturing the same |
| 08/14/2001 | US6274474 Method of forming BGA interconnections having mixed solder profiles |
| 08/14/2001 | US6274473 Flip chip packages |
| 08/14/2001 | US6274472 Tungsten interconnect method |
| 08/14/2001 | US6274471 Method for making high-aspect-ratio contacts on integrated circuits using a borderless pre-opened hard-mask technique |
| 08/14/2001 | US6274470 Method for fabricating a semiconductor device having a metallic silicide layer |
| 08/14/2001 | US6274469 Process using a plug as a mask for a gate |
| 08/14/2001 | US6274468 Method of manufacturing borderless contact |
| 08/14/2001 | US6274467 Dual work function gate conductors with self-aligned insulating cap |
| 08/14/2001 | US6274466 Method of fabricating a semiconductor device |
| 08/14/2001 | US6274465 DC electric field assisted anneal |
| 08/14/2001 | US6274464 Epitaxial cleaning process using HCL and N-type dopant gas to reduce defect density and auto doping effects |
| 08/14/2001 | US6274463 Fabrication of a photoconductive or a cathoconductive device using lateral solid overgrowth method |
| 08/14/2001 | US6274461 Method for depositing layers of high quality semiconductor material |
| 08/14/2001 | US6274460 Defect gettering by induced stress |
| 08/14/2001 | US6274459 Method for non mass selected ion implant profile control |
| 08/14/2001 | US6274458 Method of gas cleaving a semiconductor product |
| 08/14/2001 | US6274457 Method for manufacturing an isolation trench having plural profile angles |
| 08/14/2001 | US6274456 Monolithic device isolation by buried conducting walls |
| 08/14/2001 | US6274455 Method for isolating semiconductor device |
| 08/14/2001 | US6274454 Method for fabricating dielectric capacitor |
| 08/14/2001 | US6274453 Memory cell configuration and production process therefor |
| 08/14/2001 | US6274452 Semiconductor device having multilayer interconnection structure and method for manufacturing the same |
| 08/14/2001 | US6274451 Method of fabricating a gate-control electrode for an IGBT transistor |
| 08/14/2001 | US6274450 Method for implementing metal oxide semiconductor field effect transistor |
| 08/14/2001 | US6274449 Method of pocket implant modeling for a CMOS process |
| 08/14/2001 | US6274448 Method of suppressing junction capacitance of source/drain regions |
| 08/14/2001 | US6274447 Semiconductor device comprising a MOS element and a fabrication method thereof |
| 08/14/2001 | US6274446 Method for fabricating abrupt source/drain extensions with controllable gate electrode overlap |
| 08/14/2001 | US6274445 Method of manufacturing shallow source/drain junctions in a salicide process |
| 08/14/2001 | US6274444 Method for forming mosfet |
| 08/14/2001 | US6274443 Simplified graded LDD transistor using controlled polysilicon gate profile |
| 08/14/2001 | US6274442 Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same |
| 08/14/2001 | US6274441 Method of forming bitline diffusion halo under gate conductor ledge |
| 08/14/2001 | US6274440 Manufacturing of cavity fuses on gate conductor level |
| 08/14/2001 | US6274439 Process for fabricating semiconductor device with field effect transistor changeable in threshold voltage with hydrogen ion after formation of wirings |
| 08/14/2001 | US6274438 Method of manufacturing contact programmable ROM |
| 08/14/2001 | US6274437 Trench gated power device fabrication by doping side walls of partially filled trench |
| 08/14/2001 | US6274436 Method for forming minute openings in semiconductor devices |
| 08/14/2001 | US6274435 High performance MIM (MIP) IC capacitor process |
| 08/14/2001 | US6274434 Method of making memory cell with shallow trench isolation |
| 08/14/2001 | US6274433 Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices |
| 08/14/2001 | US6274432 Method of making contactless nonvolatile semiconductor memory device having buried bit lines surrounded by grooved insulators |
| 08/14/2001 | US6274431 Method for manufacturing an integrated circuit arrangement having at least one MOS transistor |
| 08/14/2001 | US6274430 Fabrication method for a high voltage electrical erasable programmable read only memory device |
| 08/14/2001 | US6274429 Use of Si-rich oxide film as a chemical potential barrier for controlled oxidation |
| 08/14/2001 | US6274428 Method for forming a ragged polysilicon crown-shaped capacitor for a memory cell |
| 08/14/2001 | US6274427 Method of manufacturing a DRAM capacitor |
| 08/14/2001 | US6274426 Self-aligned contact process for a crown shaped dynamic random access memory capacitor structure |
| 08/14/2001 | US6274425 Method for manufacturing semiconductor device |
| 08/14/2001 | US6274424 Method for forming a capacitor electrode |
| 08/14/2001 | US6274423 Etch process for aligning a capacitor structure and an adjacent contact corridor |
| 08/14/2001 | US6274422 Method for manufacturing a semiconductor device |
| 08/14/2001 | US6274421 Method of making metal gate sub-micron MOS transistor |
| 08/14/2001 | US6274420 Sti (shallow trench isolation) structures for minimizing leakage current through drain and source silicides |
| 08/14/2001 | US6274419 Trench isolation of field effect transistors |
| 08/14/2001 | US6274418 Method of manufacturing flash memory cell |