| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 08/16/2001 | US20010014524 Forming metal contact pad on substrate, forming insulating layer on metal contact pad, removing portion of insulating layer to expose portion of metal contact pad, selectively depositing solder to form contact, annealing |
| 08/16/2001 | US20010014523 Electrode structure for semiconductor device, method for forming the same, mounted body including semiconductor device and semiconductor device |
| 08/16/2001 | US20010014522 Forming layer containing silicon, depositing metal layer over first layer, annealing metal layer in ambient having a composition selected from nitrogen, ammonia, and hydrazine, wherein a second silicide layer is formed |
| 08/16/2001 | US20010014521 Batch processing for semiconductor wafers to form aluminum nitride and titanium aluminum nitride |
| 08/16/2001 | US20010014520 Process monitoring methods in a plasma processing apparatus, monitoring units, and a sample processing method using the monitoring units |
| 08/16/2001 | US20010014519 Novel method for the formation of various oxide thicknesses on a nitride |
| 08/16/2001 | US20010014518 Method of forming a thin film transistor |
| 08/16/2001 | US20010014517 Semiconductor device and fabrication met hod thereof |
| 08/16/2001 | US20010014516 Method for manufacturing semiconductor device and ultrathin semiconductor device |
| 08/16/2001 | US20010014515 Wafer grooves for reducing semiconductor wafer warping |
| 08/16/2001 | US20010014514 Low temperature silicon wafer bond process with bulk material bond strength |
| 08/16/2001 | US20010014513 Sti divot and seam elimination |
| 08/16/2001 | US20010014512 Ultra-thin resist shallow trench process using high selectivity nitride etch |
| 08/16/2001 | US20010014511 Technique for forming shallow trench isolation structure without corner exposure and resulting structure |
| 08/16/2001 | US20010014510 Forming electrode, forming dielectric thin film by depositing amorphous tantalum oxynitride film on surface of lower electrode, supplying tantalum source gas, supplying reaction gas, forming upper electrode on upper portion of dielectric |
| 08/16/2001 | US20010014508 Method for preventing junction leakage of borderless contact |
| 08/16/2001 | US20010014507 Method of forming a dual local oxidation structure of a memory chip in a semiconductor wafer |
| 08/16/2001 | US20010014506 Method for forming an isolation region in a semiconductor device and resulting structure using a two step oxidation process |
| 08/16/2001 | US20010014505 Amorphous dielectric capacitors on silicon |
| 08/16/2001 | US20010014504 Semiconductor device with selective epitaxial growth layer and isolation method in a semiconductor device |
| 08/16/2001 | US20010014503 Nonvolatile semiconductor memory device and its manufacturing method |
| 08/16/2001 | US20010014502 Method of manufacturing nonvolatile semiconductor memory device |
| 08/16/2001 | US20010014501 Flash memory structure using sidewall floating gate having one side thereof surrounded by control gate |
| 08/16/2001 | US20010014500 Method of forming retrograde doping profile in twin well CMOS device |
| 08/16/2001 | US20010014499 Methods of forming storage capacitors in integrated circuitry memory cells and integrated circuitry |
| 08/16/2001 | US20010014498 Method and apparatus for forming an inlaid capacitor in a semiconductor wafer |
| 08/16/2001 | US20010014497 CMOS process |
| 08/16/2001 | US20010014496 Semiconductor device and a manufacturing method thereof |
| 08/16/2001 | US20010014495 Method for forming super-steep retrograded channel (SSRC) for cmos transistor using rapid laser annealing to reduce thermal budget |
| 08/16/2001 | US20010014493 Thin film semiconductor device for display and method of producing same |
| 08/16/2001 | US20010014492 Process for producing semiconductor chip |
| 08/16/2001 | US20010014491 Lead frame and manufacturing method thereof |
| 08/16/2001 | US20010014490 Method of manufacturing semiconductor integrated circuit device |
| 08/16/2001 | US20010014488 Multi chip semiconductor package and method of construction |
| 08/16/2001 | US20010014485 Method for establishing reference coordinates for a point on a component |
| 08/16/2001 | US20010014484 Having a dielectric constant of 10 or greater deposited directly on a silicon-containing electrode |
| 08/16/2001 | US20010014483 Adhesive laminated tissue layers |
| 08/16/2001 | US20010014482 Capacitors and methods of forming capacitors |
| 08/16/2001 | US20010014481 Dual tox trench dram structures and process using v-groove |
| 08/16/2001 | US20010014449 The stabilizer, reporter, and target amplicons are hybridized using electronic assistance of the microchip system so that base-stacking energies are used in discerning among other indicators such as wildtype or polymorphism sequence |
| 08/16/2001 | US20010014431 Method for decreasing surface defects of patterned resist layer |
| 08/16/2001 | US20010014428 Containing dihydroxy-1-adamantyl (meth)acrylate |
| 08/16/2001 | US20010014426 Lithography; screen printing, curing |
| 08/16/2001 | US20010014424 Photomask substrates; photolithography |
| 08/16/2001 | US20010014409 Article, method, and apparatus for electrochemical fabrication |
| 08/16/2001 | US20010014397 Method for producing a wafer support, used, in particular, in a high-temperature CVD reactor or in a high-temperature CVD process which involves the use of aggressive gases |
| 08/16/2001 | US20010014375 Pellicle case having chemical traps |
| 08/16/2001 | US20010014374 Conductive support and an insulator provided on the upper surface of the support |
| 08/16/2001 | US20010014372 Wafer is transferred to the coating unit while maintaining its temperature with high accuracy to be coated with a resist solution so that a uniform processing can be performed |
| 08/16/2001 | US20010014271 Including a transfer arm |
| 08/16/2001 | US20010014269 High throughput wafer transfer mechanism |
| 08/16/2001 | US20010014268 Multi-axis transfer arm with an extensible tracked carriage |
| 08/16/2001 | US20010014267 Wafer processing apparatus, method of operating the same and wafer detecting system |
| 08/16/2001 | US20010014266 Dual cassette load lock |
| 08/16/2001 | US20010014170 Object positioning method for a lithographic projection apparatus |
| 08/16/2001 | US20010014047 Semiconductor memory device including an SOI substrate |
| 08/16/2001 | US20010014042 Semiconductor device, semiconductor memory device and semiconductor integrated circuit device |
| 08/16/2001 | US20010014040 Semiconductor memory device having program circuit |
| 08/16/2001 | US20010014030 Layout design method on semiconductor chip for avoiding detour wiring |
| 08/16/2001 | US20010014016 Electronic circuit package assembly and method of producing the same |
| 08/16/2001 | US20010014003 Integrated power modules for plasma processing systems |
| 08/16/2001 | US20010013927 Stage apparatus, exposure apparatus using the same, and a device manufacturing method |
| 08/16/2001 | US20010013925 Lithographic projection apparatus having a temperature controlled heat shield |
| 08/16/2001 | US20010013832 Device and method for monitoring the operation of an industrial installation |
| 08/16/2001 | US20010013799 Circuit for voltage level detection |
| 08/16/2001 | US20010013787 Needle load measuring method, needle load setting method and needle load detecting mechanism |
| 08/16/2001 | US20010013776 Magnetic field sensor with perpendicular axis sensitivity, comprising a giant magnetoresistance material of a spin tunnel junction |
| 08/16/2001 | US20010013773 Configuration with a plurality of sensor groups and method of determining its intactness |
| 08/16/2001 | US20010013772 Chuck device and chuck method |
| 08/16/2001 | US20010013684 Edge handling wafer chuck |
| 08/16/2001 | US20010013674 Resin-molding method, molding dies and circuit base member |
| 08/16/2001 | US20010013662 Pad layout and lead layout in semiconductor device |
| 08/16/2001 | US20010013661 Semiconductor device |
| 08/16/2001 | US20010013660 Beol decoupling capacitor |
| 08/16/2001 | US20010013659 Semiconductor memory device having a multi-layer interconnection structure suitable for merging with logic |
| 08/16/2001 | US20010013658 Integrated circuit and method for its manufacture |
| 08/16/2001 | US20010013657 Semiconductor device and method of manufacturing the same |
| 08/16/2001 | US20010013656 Semiconductor device and method of producing the same |
| 08/16/2001 | US20010013655 Methods of making microelectronic connections with liquid conductive elements |
| 08/16/2001 | US20010013654 Ball grid package with multiple power/ ground planes |
| 08/16/2001 | US20010013653 Array of electrodes reliable, durable and economical and process for fabrication thereof |
| 08/16/2001 | US20010013652 Semiconductor device free from short-circuit between bump electrodes and separation from circuit board and process of fabrication thereof |
| 08/16/2001 | US20010013651 Semiconductor device and manufacturing method therefor |
| 08/16/2001 | US20010013650 Circuit interconnect providing reduced crosstalk and simultaneous switching noise |
| 08/16/2001 | US20010013649 Encapsulated transfer molding of a semiconductor die with attached heat sink |
| 08/16/2001 | US20010013648 Method of manufacturing a ceramic package utilizing green sheets |
| 08/16/2001 | US20010013644 Chip carriers with enhanced wire bondabi lity |
| 08/16/2001 | US20010013641 Mounting substrate and mounting method for semiconductor device |
| 08/16/2001 | US20010013639 Ball-grid-array semiconductor with protruding terminals |
| 08/16/2001 | US20010013638 Dual layer etch stop barrier |
| 08/16/2001 | US20010013637 Iridium conductive electrode/barrier structure and method for same |
| 08/16/2001 | US20010013636 A self-aligned, sub-minimum isolation ring |
| 08/16/2001 | US20010013635 Bipolar transistor with trenched-groove isolation regions |
| 08/16/2001 | US20010013634 High-voltage integrated vertical resistor and manufacturing process thereof |
| 08/16/2001 | US20010013633 Integrated device with trimming elements |
| 08/16/2001 | US20010013632 Programmable integrated passive devices |
| 08/16/2001 | US20010013631 Trench isolation for semiconductor devices |
| 08/16/2001 | US20010013630 Isolation in micromachined single crystal silicon using deep trench insulation |
| 08/16/2001 | US20010013629 Multi-layer gate dielectric |
| 08/16/2001 | US20010013628 Asymmetric mosfet devices |