Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2001
08/21/2001US6278628 Semiconductor integrated circuit
08/21/2001US6278618 Substrate strips for use in integrated circuit packaging
08/21/2001US6278600 Electrostatic chuck with improved temperature control and puncture resistance
08/21/2001US6278554 Image pickup optical system
08/21/2001US6278550 Beam homogenizer
08/21/2001US6278516 Projection exposure apparatus and method of producing a device using a projection exposure apparatus
08/21/2001US6278514 Exposure apparatus
08/21/2001US6278318 Booster circuit associated with low-voltage power source
08/21/2001US6278287 Isolated well transistor structure for mitigation of single event upsets
08/21/2001US6278284 Testing IC socket
08/21/2001US6278267 Method of determining impurity content and apparatus for the same
08/21/2001US6278231 An anodized film on a substrate surface; said film having a nanohole with diameters that differ at the surface of film and the surface of substrate and having a constriction of the nanohole between the surfaces; uniform shape and depth
08/21/2001US6278193 Optical sensing method to place flip chips
08/21/2001US6278192 Semiconductor device with encapsulating material composed of silica
08/21/2001US6278191 Bond pad sealing using wire bonding
08/21/2001US6278189 High density integrated circuits using tapered and self-aligned contacts
08/21/2001US6278188 Semiconductor constructions comprising aluminum-containing layers
08/21/2001US6278187 Semiconductor device having an improved interlayer conductor connections and a manufacturing method thereof
08/21/2001US6278186 Parasitic current barriers
08/21/2001US6278185 Semi-additive process (SAP) architecture for organic leadless grid array packages
08/21/2001US6278184 Solder disc connection
08/21/2001US6278183 Semiconductor device and method for manufacturing the same
08/21/2001US6278182 Lead frame type semiconductor package
08/21/2001US6278181 Stacked multi-chip modules using C4 interconnect technology having improved thermal management
08/21/2001US6278180 Ball-grid-array-type semiconductor device and its fabrication method and electronic device
08/21/2001US6278177 Substrateless chip scale package and method of making same
08/21/2001US6278176 Semiconductor device and process for producing the same
08/21/2001US6278175 Leadframe alteration to direct compound flow into package
08/21/2001US6278174 Integrated circuit insulator and structure using low dielectric insulator material including HSQ and fluorinated oxide
08/21/2001US6278173 Semiconductor device, its manufacturing method and substrate for manufacturing a semiconductor device
08/21/2001US6278172 Semiconductor device having high-density capacitor elements and manufacturing method thereof
08/21/2001US6278166 Use of nitric oxide surface anneal to provide reaction barrier for deposition of tantalum pentoxide
08/21/2001US6278165 MIS transistor having a large driving current and method for producing the same
08/21/2001US6278164 Semiconductor device with gate insulator formed of high dielectric film
08/21/2001US6278163 HV transistor structure and corresponding manufacturing method
08/21/2001US6278162 ESD protection for LDD devices
08/21/2001US6278161 Transistor
08/21/2001US6278160 Semiconductor device having a reliably-formed narrow active region
08/21/2001US6278158 Voltage variable capacitor with improved C-V linearity
08/21/2001US6278156 Dielectric separate type semiconductor device
08/21/2001US6278155 P-channel MOSFET semiconductor device having a low on resistance
08/21/2001US6278154 Semiconductor apparatus and solid state imaging device
08/21/2001US6278153 Thin film capacitor formed in via
08/21/2001US6278152 Semiconductor device and method of manufacturing the same
08/21/2001US6278151 Semiconductor device having wiring detour around step
08/21/2001US6278150 Conductive layer connecting structure and method of manufacturing the same
08/21/2001US6278149 Plurality of trench capacitors used for the peripheral circuit
08/21/2001US6278148 Semiconductor device having a shielding conductor
08/21/2001US6278147 On-chip decoupling capacitor with bottom hardmask
08/21/2001US6278146 Ferroelectric capacitor and a method for manufacturing thereof
08/21/2001US6278144 Field-effect transistor and method for manufacturing the field effect transistor
08/21/2001US6278143 Semiconductor device with bipolar and J-FET transistors
08/21/2001US6278141 Enhancement-mode semiconductor device
08/21/2001US6278132 Semiconductor device and method of manufacturing the same
08/21/2001US6278131 Pixel TFT and driver TFT having different gate insulation width
08/21/2001US6278128 Semiconductor device having external connection terminals formed in two-dimensional area
08/21/2001US6278124 Electron beam blanking method and system for electron beam lithographic processing
08/21/2001US6278112 Method of setting a base energy level for an Auger electron spectroscopy analysis of a titanium nitride film, and method of analyzing the titanium nitride film
08/21/2001US6278097 Burn-in apparatus for burning-in microwave transistors
08/21/2001US6278089 Heater for use in substrate processing
08/21/2001US6277767 Irradiating; removal phthalic acid or ester
08/21/2001US6277766 Method of making fullerene-decorated nanoparticles and their use as a low dielectric constant material for semiconductor devices
08/21/2001US6277765 Low-K Dielectric layer and method of making same
08/21/2001US6277764 Forming silicon oxyfluoride dielectric
08/21/2001US6277763 Controlled etching
08/21/2001US6277762 Method for removing redeposited veils from etched platinum
08/21/2001US6277761 Method for fabricating stacked vias
08/21/2001US6277760 Method for fabricating ferroelectric capacitor
08/21/2001US6277759 For semiconductors
08/21/2001US6277758 Method of etching doped silicon dioxide with selectivity to undoped silicon dioxide with a high density plasma etcher
08/21/2001US6277757 Methods to modify wet by dry etched via profile
08/21/2001US6277756 Method for manufacturing semiconductor device
08/21/2001US6277755 Method for fabricating an interconnect
08/21/2001US6277754 Method of planarizing dielectric layer
08/21/2001US6277753 Removal of CMP residue from semiconductors using supercritical carbon dioxide process
08/21/2001US6277752 Multiple etch method for forming residue free patterned hard mask layer
08/21/2001US6277751 Method of planarization
08/21/2001US6277749 Method of manufacturing a semiconductor integrated circuit device
08/21/2001US6277747 Method for removal of etch residue immediately after etching a SOG layer
08/21/2001US6277746 Methods of reducing corrosion of materials, methods of protecting aluminum within aluminum-comprising layers from electrochemical degradation during semiconductor processing, and semicoductor processing methods of forming aluminum-comprising lines
08/21/2001US6277745 Passivation method of post copper dry etching
08/21/2001US6277744 Two-level silane nucleation for blanket tungsten deposition
08/21/2001US6277743 Method of fabricating self-aligned silicide
08/21/2001US6277742 Method of protecting tungsten plug from corroding
08/21/2001US6277741 Method and planarizing polysilicon layer
08/21/2001US6277740 Integrated circuit trenched features and method of producing same
08/21/2001US6277739 Method of forming a barrier layer underlying a tungsten plug structure in a high aspect ratio contact hole
08/21/2001US6277738 Method of manufacturing a semiconductor device capable of reducing contact resistance
08/21/2001US6277737 Semiconductor processing methods and integrated circuitry
08/21/2001US6277736 Method for forming gate
08/21/2001US6277735 Method for forming a refractory metal silicide layer
08/21/2001US6277734 Semiconductor device fabrication method
08/21/2001US6277733 Oxygen-free, dry plasma process for polymer removal
08/21/2001US6277732 Method of planarizing inter-metal dielectric layer
08/21/2001US6277730 Method of fabricating interconnects utilizing fluorine doped insulators and barrier layers
08/21/2001US6277729 Method of manufacturing transistor barrier layer
08/21/2001US6277728 Multilevel interconnect structure with low-k dielectric and method of fabricating the structure
08/21/2001US6277727 Method of forming a landing pad on a semiconductor wafer
08/21/2001US6277726 Method for decreasing contact resistance of an electrode positioned inside a misaligned via for multilevel interconnects
08/21/2001US6277725 Method for fabricating passivation layer on metal pad