Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2001
08/28/2001US6282080 Semiconductor circuit components and capacitors
08/28/2001US6281974 Method and apparatus for measurements of patterned structures
08/28/2001US6281966 Exposure apparatus and device manufacturing method
08/28/2001US6281965 Exposure method and exposure system using the exposure method
08/28/2001US6281964 Projection exposure apparatus and device manufacturing method
08/28/2001US6281962 Processing apparatus for coating substrate with resist and developing exposed resist including inspection equipment for inspecting substrate and processing method thereof
08/28/2001US6281778 Monolithic inductor with magnetic flux lines guided away from substrate
08/28/2001US6281756 Transistor with internal matching circuit
08/28/2001US6281737 Method and apparatus for reducing parasitic bipolar current in a silicon-on-insulator transistor
08/28/2001US6281733 Clock control method and integrated circuit element manufactured by using same
08/28/2001US6281713 Current sense amplifiers having equalization circuits therin that inhibit signal oscillations during active modes
08/28/2001US6281693 Semiconductor device test board and a method of testing a semiconductor device
08/28/2001US6281655 High performance stage assembly
08/28/2001US6281654 Method for making apparatus with dynamic support structure isolation and exposure method
08/28/2001US6281643 Stage apparatus
08/28/2001US6281593 SOI MOSFET body contact and method of fabrication
08/28/2001US6281592 Package structure for semiconductor chip
08/28/2001US6281591 Semiconductor apparatus and semiconductor apparatus manufacturing method
08/28/2001US6281589 System of selectively cleaning copper substrate surfaces, in-situ, to remove copper oxides
08/28/2001US6281588 Lead configurations
08/28/2001US6281587 Multi-layered coaxial interconnect structure
08/28/2001US6281586 Integrated semiconductor circuit configuration having stabilized conductor tracks
08/28/2001US6281585 Air gap dielectric in self-aligned via structures
08/28/2001US6281584 Integrated circuit with improved adhesion between interfaces of conductive and dielectric surfaces
08/28/2001US6281581 Substrate structure for improving attachment reliability of semiconductor chips and modules
08/28/2001US6281580 LSI package and inner lead wiring method for same
08/28/2001US6281579 Insert-molded leadframe to optimize interface between powertrain and driver board
08/28/2001US6281571 Semiconductor device having an external connection electrode extending through a through hole formed in a substrate
08/28/2001US6281570 Tape carrier for BGA and semiconductor device using the same
08/28/2001US6281569 Pressure-contact semiconductor device
08/28/2001US6281567 Substrate for mounting semiconductor chip with parallel conductive lines
08/28/2001US6281566 Plastic package for electronic devices
08/28/2001US6281565 Semiconductor device and method for producing the same
08/28/2001US6281564 Programmable integrated passive devices
08/28/2001US6281563 Laser programming of CMOS semiconductor devices using make-link structure
08/28/2001US6281562 Semiconductor device which reduces the minimum distance requirements between active areas
08/28/2001US6281559 Gate stack structure for variable threshold voltage
08/28/2001US6281558 Semiconductor device and manufacturing method thereof
08/28/2001US6281557 Read-only memory cell array and method for fabricating it
08/28/2001US6281556 Process for forming a low resistivity titanium silicide layer on a silicon semiconductor substrate and the resulting device
08/28/2001US6281555 Improved packing density due to an ultra shallow trench isolation structure
08/28/2001US6281552 Thin film transistors having ldd regions
08/28/2001US6281551 Back-plane for semiconductor device
08/28/2001US6281548 Power semiconductor device using semi-insulating polycrystalline silicon
08/28/2001US6281547 Power transistor cells provided with reliable trenched source contacts connected to narrower source manufactured without a source mask
08/28/2001US6281545 Multi-level, split-gate, flash memory cell
08/28/2001US6281544 Flash memory structure and method of manufacture
08/28/2001US6281543 Double layer electrode and barrier system on hemispherical grain silicon for use with high dielectric constant materials and methods for fabricating the same
08/28/2001US6281542 Flower-like capacitor structure for a memory cell
08/28/2001US6281541 Metal-oxide-metal capacitor for analog devices
08/28/2001US6281540 Semiconductor memory device having bitlines of common height
08/28/2001US6281539 Structure and process for 6F2 DT cell having vertical MOSFET and large storage capacitance
08/28/2001US6281538 Multi-layer tunneling device with a graded stoichiometry insulating layer
08/28/2001US6281537 Ferroelectric memory device guaranteeing electrical interconnection between lower capacitor electrode and contact plug and method for fabricating the same
08/28/2001US6281536 Ferroelectric memory device with improved ferroelectric capacity characteristic
08/28/2001US6281535 Three-dimensional ferroelectric capacitor structure for nonvolatile random access memory cell
08/28/2001US6281534 Low imprint ferroelectric material for long retention memory and method of making the same
08/28/2001US6281532 Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering
08/28/2001US6281531 Solid picture element
08/28/2001US6281530 LPNP utilizing base ballast resistor
08/28/2001US6281529 Semiconductor device having optimized input/output cells
08/28/2001US6281528 Ohmic contact improvement between layer of a semiconductor device
08/28/2001US6281522 First semiconductive layer of silicon carbide, a buffer layer of aluminum nitride, and a second semiconductor layer of aluminum, gallium, and indium nitride; for laser diodes; electrical and optical properties
08/28/2001US6281521 Silicon carbide horizontal channel buffered gate semiconductor devices
08/28/2001US6281520 Gate insulated field effect transistors and method of manufacturing the same
08/28/2001US6281518 Layered III-V semiconductor structures and light emitting devices including the structures
08/28/2001US6281516 FIMS transport box load interface
08/28/2001US6281513 Pattern forming method
08/28/2001US6281512 Ion implantation system having direct and alternating current sources
08/28/2001US6281511 Apparatus for forming materials
08/28/2001US6281510 Sample transferring method and sample transfer supporting apparatus
08/28/2001US6281496 Observing/forming method with focused ion beam and apparatus therefor
08/28/2001US6281479 Continual flow rapid thermal processing apparatus and method
08/28/2001US6281471 Energy-efficient, laser-based method and system for processing target material
08/28/2001US6281470 Thin film semiconductor device uniforming characteristics of semiconductor elements and manufacturing method thereof
08/28/2001US6281469 Capacitively coupled RF-plasma reactor
08/28/2001US6281452 Multi-level thin-film electronic packaging structure and related method
08/28/2001US6281450 Substrate for mounting semiconductor chips
08/28/2001US6281448 Printed circuit board and electronic components
08/28/2001US6281447 Substrate structure
08/28/2001US6281445 Device and method for connecting two electronic components
08/28/2001US6281437 Method of forming an electrical connection between a conductive member having a dual thickness substrate and a conductor and electronic package including said connection
08/28/2001US6281161 Platinum-containing materials and catalysts
08/28/2001US6281147 Plasma CVD method
08/28/2001US6281146 Plasma enhanced chemical vapor deposition (PECVD) method for forming microelectronic layer with enhanced film thickness uniformity
08/28/2001US6281145 Apparatus and method for applying process solution
08/28/2001US6281143 Method of forming borderless contact
08/28/2001US6281142 Dielectric cure for reducing oxygen vacancies
08/28/2001US6281141 Process for forming thin dielectric layers in semiconductor devices
08/28/2001US6281140 Method of reducing the roughness of a gate insulator layer after exposure of the gate insulator layer to a threshold voltage implantation procedure
08/28/2001US6281139 Wafer having smooth surface
08/28/2001US6281138 System and method for forming a uniform thin gate oxide layer
08/28/2001US6281137 Chemical treatment apparatus and chemical treatment method
08/28/2001US6281136 Apparatus for etching glass substrate
08/28/2001US6281135 Oxygen free plasma stripping process
08/28/2001US6281134 Method for combining logic circuit and capacitor
08/28/2001US6281133 Method for forming an inter-layer dielectric layer
08/28/2001US6281132 Device and method for etching nitride spacers formed upon an integrated circuit gate conductor
08/28/2001US6281131 Methods of forming electrical contacts
08/28/2001US6281127 Self-passivation procedure for a copper damascene structure