| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 09/04/2001 | US6284670 Method of etching silicon wafer and silicon wafer |
| 09/04/2001 | US6284669 Power transistor with silicided gate and contacts |
| 09/04/2001 | US6284668 Plasma polishing method |
| 09/04/2001 | US6284666 Method of reducing RIE lag for deep trench silicon etching |
| 09/04/2001 | US6284665 Method for controlling the shape of the etch front in the etching of polysilicon |
| 09/04/2001 | US6284664 Semiconductor device, and manufacturing method therefor |
| 09/04/2001 | US6284663 Method for making field effect devices and capacitors with thin film dielectrics and resulting devices |
| 09/04/2001 | US6284662 Method of forming a cobalt silicide layer by use of a TEOS through oxide film for ion-implantation process |
| 09/04/2001 | US6284661 Method and apparatus for producing a wafer |
| 09/04/2001 | US6284660 Method for improving CMP processing |
| 09/04/2001 | US6284658 Manufacturing process for semiconductor wafer |
| 09/04/2001 | US6284657 Non-metallic barrier formation for copper damascene type interconnects |
| 09/04/2001 | US6284656 Copper-polymer connections |
| 09/04/2001 | US6284655 Integraed circuits |
| 09/04/2001 | US6284654 Chemical vapor deposition process for fabrication of hybrid electrodes |
| 09/04/2001 | US6284653 Method of selectively forming a barrier layer from a directionally deposited metal layer |
| 09/04/2001 | US6284652 Adhesion promotion method for electro-chemical copper metallization in IC applications |
| 09/04/2001 | US6284651 Method for forming a contact having a diffusion barrier |
| 09/04/2001 | US6284650 Integrated tungsten-silicide processes |
| 09/04/2001 | US6284649 Chemical vapor phase growing method of a metal nitride film and a method of manufacturing an electronic device using the same |
| 09/04/2001 | US6284648 Semiconductor processing method of forming a buried contact |
| 09/04/2001 | US6284647 Method to improve the uniformity of chemical mechanical polishing |
| 09/04/2001 | US6284646 Methods of forming smooth conductive layers for integrated circuit devices |
| 09/04/2001 | US6284645 Controlling improvement of critical dimension of dual damasceue process using spin-on-glass process |
| 09/04/2001 | US6284644 IMD scheme by post-plasma treatment of FSG and TEOS oxide capping layer |
| 09/04/2001 | US6284642 Integrated method of damascene and borderless via process |
| 09/04/2001 | US6284641 Method of forming a contact using a sacrificial spacer |
| 09/04/2001 | US6284640 Manufacturing method for semiconductor device, mounting method of semiconductor device, semiconductor device, and inspecting method of semiconductor device |
| 09/04/2001 | US6284639 Method for forming a structured metallization on a semiconductor wafer |
| 09/04/2001 | US6284638 Manufacturing method of a semiconductor device |
| 09/04/2001 | US6284637 Forming integrated circuits |
| 09/04/2001 | US6284636 Tungsten gate method and apparatus |
| 09/04/2001 | US6284635 Method for forming titanium polycide gate |
| 09/04/2001 | US6284634 Method for forming metal line in semiconductor device |
| 09/04/2001 | US6284633 Method for forming a tensile plasma enhanced nitride capping layer over a gate electrode |
| 09/04/2001 | US6284632 Method for manufacturing semiconductor device with stagnated process gas |
| 09/04/2001 | US6284631 Method and device for controlled cleaving process |
| 09/04/2001 | US6284630 Method for fabrication of abrupt drain and source extensions for a field effect transistor |
| 09/04/2001 | US6284629 Method of fabricating an SOI wafer and SOI wafer fabricated by the method |
| 09/04/2001 | US6284628 Method of recycling a delaminated wafer and a silicon wafer used for the recycling |
| 09/04/2001 | US6284627 Method for wiring semi-conductor components in order to prevent product piracy and manipulation, semi-conductors component made according to this method and use of said semi-conductor component in a chip card |
| 09/04/2001 | US6284626 Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench |
| 09/04/2001 | US6284625 Method of forming a shallow groove isolation structure |
| 09/04/2001 | US6284624 Semiconductor device and method of manufacturing the same |
| 09/04/2001 | US6284623 Method of fabricating semiconductor devices using shallow trench isolation with reduced narrow channel effect |
| 09/04/2001 | US6284622 Method for filling trenches |
| 09/04/2001 | US6284621 Semiconductor structure with a dielectric layer and its producing method |
| 09/04/2001 | US6284620 Method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components |
| 09/04/2001 | US6284619 Integration scheme for multilevel metallization structures |
| 09/04/2001 | US6284618 Method of making a semiconductor device having a conductor pattern side face provided with a separate conductive sidewall |
| 09/04/2001 | US6284617 Metalization outside protective overcoat for improved capacitors and inductors |
| 09/04/2001 | US6284616 Circuit and method for reducing parasitic bipolar effects during electrostatic discharges |
| 09/04/2001 | US6284615 Method and apparatus for the selective doping of semiconductor material by ion implantation |
| 09/04/2001 | US6284614 Method of manufacturing semiconductor device in which damage to gate insulating film can be reduced |
| 09/04/2001 | US6284613 Method for forming a T-gate for better salicidation |
| 09/04/2001 | US6284612 Process to fabricate ultra-short channel MOSFETs with self-aligned silicide contact |
| 09/04/2001 | US6284611 Method for salicide process using a titanium nitride barrier layer |
| 09/04/2001 | US6284610 Method to reduce compressive stress in the silicon substrate during silicidation |
| 09/04/2001 | US6284609 Method to fabricate a MOSFET using selective epitaxial growth to form lightly doped source/drain regions |
| 09/04/2001 | US6284608 Method for making accumulation mode N-channel SOI |
| 09/04/2001 | US6284607 Method of making high-voltage HV transistors with drain extension in a CMOS process of the dual gate type with silicide |
| 09/04/2001 | US6284606 Forming dielectric mask on semiconductor substrate; preferential dry anisotropic etching |
| 09/04/2001 | US6284605 Method for fabricating semiconductor power integrated circuit |
| 09/04/2001 | US6284603 Flash memory cell structure with improved channel punch-through characteristics |
| 09/04/2001 | US6284602 Process to reduce post cycling program VT dispersion for NAND flash memory devices |
| 09/04/2001 | US6284600 Species implantation for minimizing interface defect density in flash memory devices |
| 09/04/2001 | US6284599 Method to fabricate a semiconductor resistor in embedded flash memory application |
| 09/04/2001 | US6284598 Method of manufacturing a flash memory cell having inter-poly-dielectric isolation |
| 09/04/2001 | US6284597 Method of fabricating flash memory |
| 09/04/2001 | US6284596 Method of forming split-gate flash cell for salicide and self-align contact |
| 09/04/2001 | US6284595 Method for fabricating stacked capacitor having excellent anti-oxidation property |
| 09/04/2001 | US6284594 Formation of an interpoly capacitor structure using a chemical mechanical polishing procedure |
| 09/04/2001 | US6284593 Method for shallow trench isolated, contacted well, vertical MOSFET DRAM |
| 09/04/2001 | US6284592 Method for fabricating a semiconductor device |
| 09/04/2001 | US6284591 Formation method of interconnection in semiconductor device |
| 09/04/2001 | US6284590 Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors |
| 09/04/2001 | US6284589 Method of fabricating concave capacitor including adhesion spacer |
| 09/04/2001 | US6284588 Forming barium strontium titanate |
| 09/04/2001 | US6284587 Fabricating method for semiconductor device |
| 09/04/2001 | US6284586 Integrated circuit device and method of making the same using chemical mechanical polishing to remove material in two layers following masking |
| 09/04/2001 | US6284585 Electronic memory device having bit lines with block selector switches |
| 09/04/2001 | US6284584 Method of masking for periphery salicidation of active regions |
| 09/04/2001 | US6284583 Semiconductor device and method of manufacturing the same |
| 09/04/2001 | US6284581 Integration of bipolar and CMOS devices for sub-0.1 micrometer transistors |
| 09/04/2001 | US6284580 Method for manufacturing a MOS transistor having multi-layered gate oxide |
| 09/04/2001 | US6284579 Drain leakage reduction by indium transient enchanced diffusion (TED) for low power applications |
| 09/04/2001 | US6284578 MOS transistors having dual gates and self-aligned interconnect contact windows |
| 09/04/2001 | US6284577 Overcoating substrate with electroconductive film; activation of argon plasma; anisotropic etching using halide |
| 09/04/2001 | US6284576 Manufacturing method of a thin-film transistor of a reverse staggered type |
| 09/04/2001 | US6284575 Method of making a semiconductor device having fuses for repair |
| 09/04/2001 | US6284573 Wafer level fabrication and assembly of chip scale packages |
| 09/04/2001 | US6284572 Boat and assembly method for ball grid array packages |
| 09/04/2001 | US6284570 Method of manufacturing a semiconductor component from a conductive substrate containing a plurality of vias |
| 09/04/2001 | US6284569 Method of manufacturing a flexible integrated circuit package utilizing an integrated carrier ring/stiffener |
| 09/04/2001 | US6284568 Method and system for producing semiconductor device |
| 09/04/2001 | US6284567 Microsensor, and packaging method therefor |
| 09/04/2001 | US6284566 Chip scale package and method for manufacture thereof |
| 09/04/2001 | US6284565 Method of resin-encapsulating semiconductor chip and mold-releasing film used for the method |
| 09/04/2001 | US6284564 HDI chip attachment method for reduced processing |
| 09/04/2001 | US6284562 Thin film transistors |