Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2001
09/11/2001US6288935 Nonvolatile semiconductor memory device for storing multivalued data
09/11/2001US6288931 Ferroelectric memory device having cell groups containing capacitors commonly coupled to transistor
09/11/2001US6288927 Semiconductor memory device with column gate and equalizer circuitry
09/11/2001US6288926 Static semiconductor memory device and fabricating method thereof
09/11/2001US6288925 System with meshed power and signal buses on cell array
09/11/2001US6288650 Device and method for monitoring the operation of an industrial installation
09/11/2001US6288601 Boosted potential generating circuit
09/11/2001US6288586 Circuit for standby current reduction
09/11/2001US6288561 Method and apparatus for probing, testing, burn-in, repairing and programming of integrated circuits in a closed environment using a single apparatus
09/11/2001US6288557 Probe station having inner and outer shielding
09/11/2001US6288556 Method of electrical measurement of misregistration of patterns
09/11/2001US6288537 Eddy current probe with foil sensor mounted on flexible probe tip and method of use
09/11/2001US6288493 Antenna device for generating inductively coupled plasma
09/11/2001US6288453 Alignment of openings in semiconductor fabrication
09/11/2001US6288452 Semiconductor device including registration accuracy marks
09/11/2001US6288451 Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength
09/11/2001US6288450 Wiring structure for semiconductor device
09/11/2001US6288449 Integrated circuit device with aspect ratio of up to about 15:1 and a metal stack within made of layers of tantalum, tantalum nitride, titanium nitride and copper; at least one of the layers is formed by chemical vapor deposition
09/11/2001US6288448 Semiconductor interconnect barrier of boron silicon nitride and manufacturing method therefor
09/11/2001US6288447 Semiconductor device including a plurality of interconnection layers
09/11/2001US6288446 Semiconductor device with pillar-shaped capacitor storage node
09/11/2001US6288445 Semiconductor device
09/11/2001US6288444 Semiconductor device and method of producing the same
09/11/2001US6288443 Chip module and manufacture of same
09/11/2001US6288442 Integrated circuit with oxidation-resistant polymeric layer
09/11/2001US6288441 Die paddle clamping method for wire bond enhancement
09/11/2001US6288439 Tape carrier package for a semiconductor device
09/11/2001US6288438 Semiconductor device including insulation film and fabrication method thereof
09/11/2001US6288436 Mixed fuse technologies
09/11/2001US6288433 Field effect transistor having improved hot carrier immunity
09/11/2001US6288432 Semiconductor fabrication employing a post-implant anneal within a low temperature, high pressure nitrogen ambient to improve channel and gate oxide reliability
09/11/2001US6288431 Semiconductor device and a method of manufacturing the same
09/11/2001US6288430 Semiconductor device having silicide layer with siliconrich region and method for making the same
09/11/2001US6288429 Semiconductor device
09/11/2001US6288428 Semiconductor integrated circuit device for disk drive apparatus
09/11/2001US6288427 Silicon-germanium BiCMOS on SOI
09/11/2001US6288426 Thermal conductivity enhanced semiconductor structures and fabrication processes
09/11/2001US6288425 SOI-MOSFET device
09/11/2001US6288424 Semiconductor device having LDMOS transistors and a screening layer
09/11/2001US6288423 Composite gate structure memory cell having increased capacitance
09/11/2001US6288422 Structure and process for fabricating a 6F2 DRAM cell having vertical MOSFET and large trench capacitance
09/11/2001US6288420 Conductive barrier layers suppress diffusion of iridium into silicon substrates; heat resistant when annealed in oxygen; electrodes of ferroelectric capcitors; stability; iridium silicide prevention
09/11/2001US6288419 Low resistance gate flash memory
09/11/2001US6288413 Thin film transistor and method for producing same
09/11/2001US6288412 Thin film transistors for display devices having two polysilicon active layers of different thicknesses
09/11/2001US6288407 Electron beam-writing apparatus and electron beam-writing method
09/11/2001US6288376 Method and apparatus for melting a bump by induction heating
09/11/2001US6288368 Vacuum heating furnace with tapered portion
09/11/2001US6288357 Ion milling planarization of semiconductor workpieces
09/11/2001US6288325 A single or dual layer front contact is positioned on a substrate with at least one amorphous silicon containing thin film semiconductor is deposited on it; stability, quality, durability, and performance
09/11/2001US6287991 Method for producing semiconductor device including step for removing contaminant
09/11/2001US6287990 CVD plasma assisted low dielectric constant films
09/11/2001US6287989 Coating wafer surface with planar layer of short chain inorganic fluid polymer formed by reacting gaseous hydrogen peroxide and silicon
09/11/2001US6287988 Semiconductor device manufacturing method, semiconductor device manufacturing apparatus and semiconductor device
09/11/2001US6287987 Method and apparatus for deposition of porous silica dielectrics
09/11/2001US6287986 Sputtering film forming method, sputtering film forming equipment, and semiconductor device manufacturing method
09/11/2001US6287985 Process for applying a molten droplet coating for integrated circuits
09/11/2001US6287984 Apparatus and method for manufacturing semiconductor device
09/11/2001US6287983 Selective nitride etching with silicate ion pre-loading
09/11/2001US6287982 Method of removing a portion of a silicon oxide form over stacked polysilicon and silicide layers by using hydrofluorine (HF) solution
09/11/2001US6287981 Electrode for generating a plasma and a plasma processing apparatus using the same
09/11/2001US6287980 Plasma processing method and plasma processing apparatus
09/11/2001US6287979 Method for forming an air gap as low dielectric constant material using buckminsterfullerene as a porogen in an air bridge or a sacrificial layer
09/11/2001US6287978 Method of etching a substrate
09/11/2001US6287977 Method and apparatus for forming improved metal interconnects
09/11/2001US6287976 Plasma processing methods and apparatus
09/11/2001US6287975 Placing a semiconductor substrate with a hard mask comprised of a reactive metal or its oxide, nitride, fluoride, boride and/or carbide in a chamber and etching the wafer
09/11/2001US6287974 Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features
09/11/2001US6287973 Method for forming interconnection structure
09/11/2001US6287972 System and method for residue entrapment utilizing a polish and sacrificial fill for semiconductor fabrication
09/11/2001US6287971 Method for forming a cell capacitor in DRAM device
09/11/2001US6287970 Method of making a semiconductor with copper passivating film
09/11/2001US6287968 Method of defining copper seed layer for selective electroless plating processing
09/11/2001US6287967 Self-aligned silicide process
09/11/2001US6287966 Vacuum bake step of semiconductor substrate prior to pre-metal hydrogen fluoride dip during the silicon-ion mixing, then depositing titanium, doping, annealing, etching to form self-aligned silicide in the contact areas
09/11/2001US6287965 Method of forming metal layer using atomic layer deposition and semiconductor device having the metal layer as barrier metal layer or upper or lower electrode of capacitor
09/11/2001US6287964 Method for forming a metallization layer of a semiconductor device
09/11/2001US6287963 Method for forming a metal contact
09/11/2001US6287962 Method for making a novel graded silicon nitride/silicon oxide (SNO) hard mask for improved deep sub-micrometer semiconductor processing
09/11/2001US6287961 Dual damascene patterned conductor layer formation method without etch stop layer
09/11/2001US6287960 Self aligned dual inlaid patterning and etching
09/11/2001US6287959 Deep submicron metallization using deep UV photoresist
09/11/2001US6287958 Method of manufacturing a self-aligned etch stop for polycrystalline silicon plugs on a semiconductor device
09/11/2001US6287957 Self-aligned contact process
09/11/2001US6287956 Comprising plurality of interconnecting layers formed on semiconductor substrate, fluorine-doped oxide film for burying portions between interconnecting layers, oxide film formed on fluorine-doped oxide film, having planarized surface
09/11/2001US6287955 Integrated circuits with multiple low dielectric-constant inter-metal dielectrics
09/11/2001US6287954 Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity
09/11/2001US6287953 Minimizing transistor size in integrated circuits
09/11/2001US6287952 Method of etching self-aligned vias to metal using a silicon nitride spacer
09/11/2001US6287951 Process for forming a combination hardmask and antireflective layer
09/11/2001US6287950 Bonding pad structure and manufacturing method thereof
09/11/2001US6287948 Semiconductor device and method for making pattern data
09/11/2001US6287946 Fabrication of low resistance, non-alloyed, ohmic contacts to InP using non-stoichiometric InP layers
09/11/2001US6287944 Polycrystalline semiconductor device and its manufacture method
09/11/2001US6287943 Deposition of semiconductor layer by plasma process
09/11/2001US6287942 Hermetic chip and method of manufacture
09/11/2001US6287941 Surface finishing of SOI substrates using an EPI process
09/11/2001US6287940 Forming thermosensitive and heat resistant microstructures on separate substrates, then joining them with bonding material
09/11/2001US6287939 Method for fabricating a shallow trench isolation which is not susceptible to buried contact trench formation
09/11/2001US6287938 Method for manufacturing shallow trench isolation in semiconductor device