| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 09/18/2001 | US6291814 Slit valve with safety detect device |
| 09/18/2001 | US6291801 Continual flow rapid thermal processing apparatus and method |
| 09/18/2001 | US6291800 Heat treatment apparatus and substrate processing system |
| 09/18/2001 | US6291799 Process and arrangement for heat treatment of two-dimensional objects |
| 09/18/2001 | US6291793 Inductively coupled plasma reactor with symmetrical parallel multiple coils having a common RF terminal |
| 09/18/2001 | US6291777 Conductive feed-through for creating a surface electrode connection within a dielectric body and method of fabricating same |
| 09/18/2001 | US6291776 Thermal deformation management for chip carriers |
| 09/18/2001 | US6291775 Flip chip bonding land waving prevention pattern |
| 09/18/2001 | US6291628 Solvent systems for low dielectric constant polymeric materials |
| 09/18/2001 | US6291619 Heat resistance |
| 09/18/2001 | US6291557 Alkali-soluble adhesive agent |
| 09/18/2001 | US6291410 Compositions for the stripping of photoresists in the fabrication of integrated circuits |
| 09/18/2001 | US6291367 Method for depositing a selected thickness of an interlevel dielectric material to achieve optimum global planarity on a semiconductor wafer |
| 09/18/2001 | US6291366 Process of manufacturing semiconductor devices |
| 09/18/2001 | US6291365 Method for manufacturing thin gate silicon oxide layer |
| 09/18/2001 | US6291364 Method and apparatus for stabilizing high pressure oxidation of a semiconductor device |
| 09/18/2001 | US6291363 Surface treatment of DARC films to reduce defects in subsequent cap layers |
| 09/18/2001 | US6291361 Method and apparatus for high-resolution in-situ plasma etching of inorganic and metal films |
| 09/18/2001 | US6291360 Method of etching a layer |
| 09/18/2001 | US6291359 Methods of forming openings and methods of controlling the degree of taper of openings |
| 09/18/2001 | US6291358 Plasma deposition tool operating method |
| 09/18/2001 | US6291357 Method and apparatus for etching a substrate with reduced microloading |
| 09/18/2001 | US6291356 Plasma etching of silicon oxynitride and semiconductor films stacks |
| 09/18/2001 | US6291355 Method of fabricating a self-aligned contact opening |
| 09/18/2001 | US6291354 Method of fabricating a semiconductive device |
| 09/18/2001 | US6291353 Lateral patterning |
| 09/18/2001 | US6291352 Method of manufacturing a semiconductor device |
| 09/18/2001 | US6291351 Endpoint detection in chemical-mechanical polishing of cloisonne structures |
| 09/18/2001 | US6291350 Method of polishing semiconductor wafer |
| 09/18/2001 | US6291348 Method of forming Cu-Ca-O thin films on Cu surfaces in a chemical solution and semiconductor device thereby formed |
| 09/18/2001 | US6291347 Method and system for constructing semiconductor devices |
| 09/18/2001 | US6291346 Insulation of silicon substrate, contact holes and vapor deposition |
| 09/18/2001 | US6291345 Controlled-stress stable metallization for electronic and electromechanical devices |
| 09/18/2001 | US6291344 Integrated circuit with improved contact barrier |
| 09/18/2001 | US6291343 Plasma annealing of substrates to improve adhesion |
| 09/18/2001 | US6291342 Methods of forming titanium nitride composite layers using composite gases having increasing TiCl4 to NH3 ratios |
| 09/18/2001 | US6291341 Method for PECVD deposition of selected material films |
| 09/18/2001 | US6291340 Method of forming low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer |
| 09/18/2001 | US6291339 Bilayer interlayer dielectric having a substantially uniform composite interlayer dielectric constant over pattern features of varying density and method of making the same |
| 09/18/2001 | US6291338 Method of fabricating self-aligned polysilicon via plug |
| 09/18/2001 | US6291337 Elimination of cracks generated after a rapid thermal process step of a semiconductor wafer |
| 09/18/2001 | US6291336 AlCu metal deposition for robust Rc via performance |
| 09/18/2001 | US6291335 Locally folded split level bitline wiring |
| 09/18/2001 | US6291334 Etch stop layer for dual damascene process |
| 09/18/2001 | US6291333 Method of fabricating dual damascene structure |
| 09/18/2001 | US6291332 Electroless plated semiconductor vias and channels |
| 09/18/2001 | US6291331 Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue |
| 09/18/2001 | US6291330 Method of fabricating gate structure to reduce stress production |
| 09/18/2001 | US6291329 Protective oxide buffer layer for ARC removal |
| 09/18/2001 | US6291328 Opto-electronic device with self-aligned ohmic contact layer |
| 09/18/2001 | US6291327 Optimization of S/D annealing to minimize S/D shorts in memory array |
| 09/18/2001 | US6291326 Pre-semiconductor process implant and post-process film separation |
| 09/18/2001 | US6291325 Asymmetric MOS channel structure with drain extension and method for same |
| 09/18/2001 | US6291324 Method of modeling IC substrate noises utilizing improved doping profile access |
| 09/18/2001 | US6291323 Method of fabrication of semiconductor structures by ion implantation |
| 09/18/2001 | US6291321 Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization |
| 09/18/2001 | US6291319 Method for fabricating a semiconductor structure having a stable crystalline interface with silicon |
| 09/18/2001 | US6291318 Growth of GaN on sapphire with MSE grown buffer layer |
| 09/18/2001 | US6291316 Method for fabricating passivated semiconductor devices |
| 09/18/2001 | US6291315 Method for etching trench in manufacturing semiconductor devices |
| 09/18/2001 | US6291314 Controlled cleavage process and device for patterned films using a release layer |
| 09/18/2001 | US6291313 Method and device for controlled cleaving process |
| 09/18/2001 | US6291312 Method for forming pullback opening above shallow trenc isolation structure |
| 09/18/2001 | US6291311 Semiconductor device and method for producing same |
| 09/18/2001 | US6291310 Method of increasing trench density for semiconductor |
| 09/18/2001 | US6291309 Semiconductor device and method for manufacturing the same |
| 09/18/2001 | US6291308 Mask ROM fabrication method |
| 09/18/2001 | US6291307 Method and structure to make planar analog capacitor on the top of a STI structure |
| 09/18/2001 | US6291306 Method of improving the voltage coefficient of resistance of high polysilicon resistors |
| 09/18/2001 | US6291305 Method for implementing resistance, capacitance and/or inductance in an integrated circuit |
| 09/18/2001 | US6291304 Method of fabricating a high voltage transistor using P+ buried layer |
| 09/18/2001 | US6291303 Method for manufacturing a bipolar junction device |
| 09/18/2001 | US6291302 Selective laser anneal process using highly reflective aluminum mask |
| 09/18/2001 | US6291301 Fabrication method of a gate junction conductive structure |
| 09/18/2001 | US6291300 Manufacturing method of semiconductor devices |
| 09/18/2001 | US6291299 Method for making MOS transistors |
| 09/18/2001 | US6291298 Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses |
| 09/18/2001 | US6291297 Flash memory cell with self-aligned gates and fabrication process |
| 09/18/2001 | US6291296 Method for removing anti-reflective coating layer using plasma etch process before contact CMP |
| 09/18/2001 | US6291295 Forming multilayer elements for capacitors on glass |
| 09/18/2001 | US6291294 Method for making a stack bottom storage node having reduced crystallization of amorphous polysilicon |
| 09/18/2001 | US6291293 Method for fabricating an open can-type stacked capacitor on an uneven surface |
| 09/18/2001 | US6291292 Method for fabricating a semiconductor memory device |
| 09/18/2001 | US6291291 Semiconductor device and method of manufacturing the same |
| 09/18/2001 | US6291290 Thin film capacitor with an improved top electrode and method of forming the same |
| 09/18/2001 | US6291289 Method of forming DRAM trench capacitor with metal layer over hemispherical grain polysilicon |
| 09/18/2001 | US6291288 Method of fabricating a thin and structurally-undefective dielectric structure for a storage capacitor in dynamic random-access memory |
| 09/18/2001 | US6291287 Method for producing a memory cell |
| 09/18/2001 | US6291286 Two-step strap implantation of making deep trench capacitors for DRAM cells |
| 09/18/2001 | US6291285 Method for protecting gate oxide layer and monitoring damage |
| 09/18/2001 | US6291284 Method of fabricating semiconductor device |
| 09/18/2001 | US6291283 Forming semiconductors with substrates, layers of suboxides of hafnium, zirconium, lanthanium, yttritium, scandium and cerium metals on substrates |
| 09/18/2001 | US6291282 Method of forming dual metal gate structures or CMOS devices |
| 09/18/2001 | US6291281 Method of fabricating protection structure |
| 09/18/2001 | US6291280 CMOS imager cell having a buried contact and method of fabrication |
| 09/18/2001 | US6291279 Method for forming different types of MOS transistors on a semiconductor wafer |
| 09/18/2001 | US6291278 Method of forming transistors with self aligned damascene gate contact |
| 09/18/2001 | US6291277 Method of manufacturing a semiconductor device including etching of a stack of layers by means of photolithography |
| 09/18/2001 | US6291275 Thin film semiconductor and method for manufacturing the same, semiconductor device and method for manufacturing the same |
| 09/18/2001 | US6291274 Resin molded semiconductor device and method for manufacturing the same |