Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2001
09/25/2001US6294471 Method of eliminating dishing effect in polishing of dielectric film
09/25/2001US6294470 Slurry-less chemical-mechanical polishing
09/25/2001US6294469 Silicon wafering process flow
09/25/2001US6294468 Introducing silane initiation gases to form an amorphous, monolayer of silicon; introducing wf6 nucleation gases to form a silane reduced tungsten layer; hydrogen reducing gas flow to form a layer of hydrogen reduced bulk tungsten
09/25/2001US6294467 Process for forming fine wiring
09/25/2001US6294466 HDP-CVD apparatus and process for depositing titanium films for semiconductor devices
09/25/2001US6294465 Method for making integrated circuits having features with reduced critical dimensions
09/25/2001US6294464 Low resistance metal silicide local interconnects and a method of making
09/25/2001US6294463 Method for manufacturing diffusion barrier layer
09/25/2001US6294462 Manufacturing method of interconnection layer for semiconductor device
09/25/2001US6294461 Improved junctions are provided between an igfet device and substuent metallization layers.
09/25/2001US6294460 Semiconductor manufacturing method using a high extinction coefficient dielectric photomask
09/25/2001US6294459 Anti-reflective coatings and methods for forming and using same
09/25/2001US6294458 Semiconductor device adhesive layer structure and process for forming structure
09/25/2001US6294457 Optimized IMD scheme for using organic low-k material as IMD layer
09/25/2001US6294456 Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule
09/25/2001US6294454 Method for manufacturing a bed structure underlying electrode pad of semiconductor device
09/25/2001US6294451 Semiconductor device and method for manufacturing the same
09/25/2001US6294450 Nanoscale patterning for the formation of extensive wires
09/25/2001US6294449 Self-aligned contact for closely spaced transistors
09/25/2001US6294448 Depositing a layer of resist protection oxide (rpo) including a surface of said partially completed gate electrode; performing an impurity implant of arsenic (as) or boron (bf2) into a surface of said substrate; pre-metal wet dip
09/25/2001US6294447 Method of making devices having thin dielectric layers
09/25/2001US6294446 Methods of manufacturing a high electron mobility transistor with a T-shaped gate electrode
09/25/2001US6294445 Single mask process for manufacture of fast recovery diode
09/25/2001US6294444 Method for manufacturing silicon carbide semiconductor device
09/25/2001US6294443 Method of epitaxy on a silicon substrate comprising areas heavily doped with boron
09/25/2001US6294442 Method for the formation of a polysilicon layer with a controlled, small silicon grain size during semiconductor device fabrication
09/25/2001US6294441 Method of manufacturing a semiconductor device
09/25/2001US6294440 Semiconductor substrate, light-emitting device, and method for producing the same
09/25/2001US6294439 Method of dividing a wafer and method of manufacturing a semiconductor device
09/25/2001US6294438 Semiconductor device having capacitor and manufacturing method thereof
09/25/2001US6294437 Method of manufacturing crown-shaped DRAM capacitor
09/25/2001US6294436 Method for fabrication of enlarged stacked capacitors using isotropic etching
09/25/2001US6294435 Method of reducing word line resistance and contact resistance
09/25/2001US6294434 Method of forming a metal silicide layer on a polysilicon gate structure and on a source/drain region of a MOSFET device
09/25/2001US6294433 Gate re-masking for deeper source/drain co-implantation processes
09/25/2001US6294432 Super halo implant combined with offset spacer process
09/25/2001US6294431 Process of manufacture of a non-volatile memory with electric continuity of the common source lines
09/25/2001US6294430 Nitridization of the pre-ddi screen oxide
09/25/2001US6294429 Method of forming a point on a floating gate for electron injection
09/25/2001US6294428 Method of forming a flash memory device
09/25/2001US6294427 Non-volatile semiconductor memory device and fabrication method thereof
09/25/2001US6294426 Method of fabricating a capacitor under bit line structure with increased capacitance without increasing the aspect ratio for a dry etched bit line contact hole
09/25/2001US6294425 Methods of forming integrated circuit capacitors by electroplating electrodes from seed layers
09/25/2001US6294424 Method for fabricating a semiconductor device
09/25/2001US6294423 Method for forming and filling isolation trenches
09/25/2001US6294422 Semiconductor device with high integration density and improved performance
09/25/2001US6294420 Integrated circuit capacitor
09/25/2001US6294419 Structure and method for improved latch-up using dual depth STI with impurity implant
09/25/2001US6294418 Circuits and methods using vertical complementary transistors
09/25/2001US6294416 Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts
09/25/2001US6294415 Method of fabricating a MOS transistor
09/25/2001US6294414 Method of fabricating heterointerface devices having diffused junctions
09/25/2001US6294413 Method for fabricating a SOI (silicon on insulator) device
09/25/2001US6294412 Silicon based lateral tunneling memory cell
09/25/2001US6294411 Method for molding a semiconductor device utilizing a satin finish
09/25/2001US6294410 Plastic lead frames for semiconductor devices, packages including same, and methods of fabrication
09/25/2001US6294409 Method of forming a constricted-mouth dimple structure on a leadframe die pad
09/25/2001US6294407 Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same
09/25/2001US6294405 Method of forming semiconductor device having a sub-chip-scale package structure
09/25/2001US6294402 Method for attaching an integrated circuit chip to a substrate and an integrated circuit chip useful therein
09/25/2001US6294401 Nanoparticle-based electrical, chemical, and mechanical structures and methods of making same
09/25/2001US6294399 Quantum thin line producing method and semiconductor device
09/25/2001US6294397 Drop-in test structure and abbreviated integrated circuit process flow for characterizing production integrated circuit process flow, topography, and equipment
09/25/2001US6294396 Monitoring barrier metal deposition for metal interconnect
09/25/2001US6294394 Ramp rate limiter to control stress during ramping
09/25/2001US6294393 Reduction of imprint in ferroelectric devices using a depoling technique
09/25/2001US6294315 Method of forming a metal wiring by a dual damascene process using a photosensitive polymer
09/25/2001US6294297 For a semiconductor manufacturing process.
09/25/2001US6294294 Implantation mask for producing a memory cell configuration
09/25/2001US6294271 Liquid epoxy resin and an inorganic filler, a specific imidazole compound having a solubility of up to 1% by weight in the epoxy resin
09/25/2001US6294270 Electronic circuit device comprising an epoxy-modified aromatic vinyl-conjugated diene block copolymer
09/25/2001US6294228 Silicon nitride film forming processes with lower temperature: unnecessary silicon nitride film is intentionally subjected to stress and cracked, whereby the unnecessary thin film is relieved from stress.
09/25/2001US6294219 Method of annealing large area glass substrates
09/25/2001US6294217 From precursor materials such as carboxylated polysiloxanes, including carboxylated polygermanosiloxanes
09/25/2001US6294106 Slurries of abrasive inorganic oxide particles and method for adjusting the abrasiveness of the particles
09/25/2001US6294105 Chemical mechanical polishing slurry and method for polishing metal/oxide layers
09/25/2001US6294102 Selective dry etch of a dielectric film
09/25/2001US6294100 Exposed die leadless plastic chip carrier
09/25/2001US6294099 Method of processing circular patterning
09/25/2001US6294059 Substrate plating apparatus
09/25/2001US6294040 Transferable resilient element for packaging of a semiconductor chip and method therefor
09/25/2001US6294027 Placing semiconductor substrate that has been subjected to a chemical mechanical polishing operation in scrubbing apparatus; scrubbing semiconductor substrate in acidic cleaning solution
09/25/2001US6294026 Distribution plate for a reaction chamber with multiple gas inlets and separate mass flow control loops
09/25/2001US6294025 Device for producing oxidic thin films
09/25/2001US6294020 Device for applying photoresist to a base body surface
09/25/2001US6294019 Method of making group III-V compound semiconductor wafer
09/25/2001US6294018 Alignment techniques for epitaxial growth processes
09/25/2001US6294016 Growing gan-based epitaxial layer while doping epitaxial layer with magnesium with hydrogen serving as carrier gas by use of metalorganic chemical vapor deposition; rapid thermal annealing in nitrogen atmosphere; nitridation and annealing
09/25/2001US6293858 Polishing device
09/25/2001US6293855 Polishing apparatus
09/25/2001US6293854 Dresser for polishing cloth and manufacturing method therefor
09/25/2001US6293853 Conditioner apparatus for chemical mechanical polishing
09/25/2001US6293849 Polishing solution supply system
09/25/2001US6293848 Composition and method for planarizing surfaces
09/25/2001US6293846 Polishing apparatus
09/25/2001US6293803 Zee electrical interconnect
09/25/2001US6293789 Semiconductor processing apparatuses
09/25/2001US6293749 Substrate transfer system for semiconductor processing equipment
09/25/2001US6293746 Transfer robot