Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2001
09/26/2001EP0708983B1 Chemical vapor deposition process for fabricating layered superlattice materials
09/26/2001CN2450782Y Double-wafer crystal
09/26/2001CN2449835Y Automatic PC board punching riveting machine
09/26/2001CN1315044A Electronic device and manufacture thereof
09/26/2001CN1315002A High resolution analytical probe station
09/26/2001CN1314991A Methods and apparatus for measuring the thickness of a film, particularly of a photoresist film on a semiconductor substrate
09/26/2001CN1314931A Water soluble resin composition
09/26/2001CN1314829A Printing of electronic circuit and components
09/26/2001CN1314715A Semiconductor device and its producing method
09/26/2001CN1314713A Vertical metal-oxide-semiconductor transistor and its producing method
09/26/2001CN1314712A Semiconductor device and its producing method
09/26/2001CN1314710A Method and structure of pole interconnection
09/26/2001CN1314709A Stress reduced line guide frame for plastic sealing
09/26/2001CN1314707A Method for forming integrated circuit device and integrated circuit device by formed said method
09/26/2001CN1314706A Method for forming element isolation zone
09/26/2001CN1314705A Buried metal double mosaic board capacitor
09/26/2001CN1314704A Tray for electronic parts
09/26/2001CN1314703A Contact switch for semiconductor device detection and its producing method
09/26/2001CN1314702A Producing system of semiconductor storage and method for producing semiconductor storage
09/26/2001CN1314701A Semiconductor substrate and its producing process
09/26/2001CN1314557A Guide type two hole vacuum valve
09/26/2001CN1314225A Structure and method for copper plating layer integrated circuit welding spot
09/26/2001CN1071919C Resistor and method for trimming resistor
09/26/2001CN1071713C Gallium arsenide, gallium phosphide backing dry treatment mehtod
09/25/2001USRE37391 Exposure method and projection exposure apparatus
09/25/2001US6295635 Adaptive Multidimensional model for general electrical interconnection structures by optimizing orthogonal expansion parameters
09/25/2001US6295633 Floor-planning technique applied to circuit design in which a circuit is divided automatically into sub-circuits that are equally matched with efficiently arranged physical blocks
09/25/2001US6295630 Method and apparatus for measuring an overlap length of MISFET, and a recording medium and a device model each carrying an extraction program for determining the overlap length
09/25/2001US6295629 Focus correcting method and method of manufacturing semiconductor device
09/25/2001US6295478 Manufacturing process change control apparatus and manufacturing process change control method
09/25/2001US6295236 Semiconductor memory of the random access type with a bus system organized in two planes
09/25/2001US6295235 Redundancy circuit of semiconductor memory
09/25/2001US6295227 Non-volatile semiconductor memory device
09/25/2001US6295224 Circuit and method of fabricating a memory cell for a static random access memory
09/25/2001US6295220 Memory bar and related circuits and methods
09/25/2001US6295200 Carrier assembly and method
09/25/2001US6295195 Capacitor having first and second protective films
09/25/2001US6295128 Optical alignment of superpositioned objects
09/25/2001US6295126 Inspection apparatus for foreign matter and pattern defect
09/25/2001US6295122 Illumination system and REMA objective with lens displacement and operating process therefor
09/25/2001US6295121 Exposure apparatus
09/25/2001US6295119 Scanning type exposure apparatus with multiple field diaphragms for providing consistent exposure
09/25/2001US6295118 Optical arrangement for exposure apparatus
09/25/2001US6294926 Very fine-grain field programmable gate array architecture and circuitry
09/25/2001US6294919 Method for nondestructive measurement of dopant concentrations and profiles in the drift region of certain semiconductor devices
09/25/2001US6294909 Electro-magnetic lithographic alignment method
09/25/2001US6294892 Method of manufacturing organic thin-film EL device
09/25/2001US6294862 Multi-cusp ion source
09/25/2001US6294841 Integrated semiconductor circuit having dummy structures
09/25/2001US6294840 Dual-thickness solder mask in integrated circuit package
09/25/2001US6294839 Apparatus and methods of packaging and testing die
09/25/2001US6294837 Semiconductor interconnect having laser machined contacts
09/25/2001US6294836 Microelectronic integrated circuit device fabrication
09/25/2001US6294835 Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof
09/25/2001US6294834 Structure of combined passive elements and logic circuit on a silicon on insulator wafer
09/25/2001US6294833 Semiconductor device and fabrication process thereof
09/25/2001US6294832 Semiconductor device having structure of copper interconnect/barrier dielectric liner/low-k dielectric trench and its fabrication method
09/25/2001US6294831 Electronic package with bonded structure and method of making
09/25/2001US6294830 Microelectronic assembly with conductive terminals having an exposed surface through a dielectric layer
09/25/2001US6294829 Multilayer quadruple gate field effect transistor structure for use in integrated circuit devices
09/25/2001US6294828 Semiconductor chip package
09/25/2001US6294827 Hybrid microwave-frequency integrated circuit
09/25/2001US6294825 Asymmetrical mold of multiple-part matrixes
09/25/2001US6294823 Integrated circuit with insulating spacers separating borderless contacts from the well
09/25/2001US6294820 Metallic oxide gate electrode stack having a metallic gate dielectric metallic gate electrode and a metallic arc layer
09/25/2001US6294819 CVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFET
09/25/2001US6294817 Source/drain-on insulator (S/DOI) field effect transistor using oxidized amorphous silicon and method of fabrication
09/25/2001US6294816 Secure integrated circuit
09/25/2001US6294815 Semiconductor device
09/25/2001US6294814 Cleaved silicon thin film with rough surface
09/25/2001US6294813 Information handling system having improved floating gate tunneling devices
09/25/2001US6294812 High density flash memory cell
09/25/2001US6294811 Two transistor EEPROM cell
09/25/2001US6294807 Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers
09/25/2001US6294806 Semiconductor memory device having silicon-on-insulator (SOI) structure and method for fabricating thereof
09/25/2001US6294805 Ferroelectric memory devices including capacitors located outside the active area and made with diffusion barrier layers
09/25/2001US6294803 Semiconductor device having trench with vertically formed field oxide
09/25/2001US6294802 Field effect transistor and method of manufacturing the same
09/25/2001US6294801 Semiconductor device with Schottky layer
09/25/2001US6294798 Integrated circuit structure comprising capacitor element and corresponding manufacturing process
09/25/2001US6294797 MOSFET with an elevated source/drain
09/25/2001US6294796 Thin film transistors and active matrices including same
09/25/2001US6294771 Electrically heated substrate with multiple ceramic parts each having different volume resitivities
09/25/2001US6294745 Solder anchor decal
09/25/2001US6294741 Electronics module having high density interconnect structures incorporating an improved dielectric lamination adhesive
09/25/2001US6294726 Silicon with structured oxygen doping, its production and use
09/25/2001US6294644 Extrusion moldability, creep and fatigue characteristics
09/25/2001US6294630 For forming high resolutin pattern
09/25/2001US6294484 Method of forming TEOS oxide films
09/25/2001US6294483 Method for preventing delamination of APCVD BPSG films
09/25/2001US6294482 Method of forming an insulating layer pattern in a liquid crystal display
09/25/2001US6294481 Semiconductor device and method for manufacturing the same
09/25/2001US6294480 Method for forming an L-shaped spacer with a disposable organic top coating
09/25/2001US6294478 Fabrication process for a semiconductor substrate
09/25/2001US6294477 Low cost high density thin film processing
09/25/2001US6294476 Plasma surface treatment method for forming patterned TEOS based silicon oxide layer with reliable via and interconnection formed therethrough
09/25/2001US6294475 Crystallographic wet chemical etching of III-nitride material
09/25/2001US6294474 Process for controlling oxide thickness over a fusible link using transient etch stops
09/25/2001US6294473 Method of polishing substrates comprising silicon dioxide and composition relating thereto
09/25/2001US6294472 Dual slurry particle sizes for reducing microscratching of wafers