Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
10/2001
10/02/2001US6297658 Wafer burn-in cassette and method of manufacturing probe card for use therein
10/02/2001US6297656 Probe-test method and prober
10/02/2001US6297611 Robot having independent end effector linkage motion
10/02/2001US6297595 Method and apparatus for generating a plasma
10/02/2001US6297594 Plasma source ion implanting apparatus using the same
10/02/2001US6297564 Semiconductor chip; contact pads with oxidation resistant coating; flip chip; thermosetting or thermplastic resin; core particles of copper, nickel, aluminum, glass or polymer plated with gold, palladium or platinum
10/02/2001US6297563 Bonding pad structure of semiconductor device
10/02/2001US6297562 Semiconductive chip having a bond pad located on an active device
10/02/2001US6297560 Semiconductor flip-chip assembly with pre-applied encapsulating layers
10/02/2001US6297559 Structure, materials, and applications of ball grid array interconnections
10/02/2001US6297558 Slurry filling a recess formed during semiconductor fabrication
10/02/2001US6297557 Reliable aluminum interconnect via structures
10/02/2001US6297555 Semiconductor with titanium nitride barrier layer
10/02/2001US6297554 Dual damascene interconnect structure with reduced parasitic capacitance
10/02/2001US6297553 Semiconductor device and process for producing the same
10/02/2001US6297545 Semiconductor device
10/02/2001US6297543 Chip scale package
10/02/2001US6297541 Semiconductor device and method for fabricating the same
10/02/2001US6297539 Zicronium or hafnium oxide doped with calcium, strontium, aluminum, lanthanum, yttrium, or scandium
10/02/2001US6297538 Metal-insulator-semiconductor field effect transistor having an oxidized aluminum nitride gate insulator formed on a gallium nitride or silicon substrate
10/02/2001US6297537 Semiconductor device and method for production thereof
10/02/2001US6297535 Transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection
10/02/2001US6297532 Semiconductor device and method of manufacturing the same
10/02/2001US6297531 High performance, low power vertical integrated CMOS devices
10/02/2001US6297530 Self aligned channel implantation
10/02/2001US6297529 Semiconductor device with multilayered gate structure
10/02/2001US6297528 Dual layer poly deposition to prevent auto-doping in mixed-mode product fabrication
10/02/2001US6297527 Platinum-rhodium alloy layer; random access memory
10/02/2001US6297526 Process for producing barrier-free semiconductor memory configurations
10/02/2001US6297525 Capacitor structures, DRAM cell structures, and integrated circuitry
10/02/2001US6297524 Multilayer capacitor structure having an array of concentric ring-shaped plates for deep sub-micron CMOS
10/02/2001US6297523 Field effect transistors
10/02/2001US6297521 Graded anti-reflective coating for IC lithography
10/02/2001US6297520 Active matrix substrate and correcting method of structural defect thereof
10/02/2001US6297519 TFT substrate with low contact resistance and damage resistant terminals
10/02/2001US6297515 Integrated acoustic thin film resonator
10/02/2001US6297510 Ion implant dose control
10/02/2001US6297480 Method and apparatus for preventing contamination in a hot plate oven
10/02/2001US6297469 Process for producing a metal-ceramic substrate
10/02/2001US6297468 Inductively coupled plasma reactor with symmetrical parallel multiple coils having a common RF terminal
10/02/2001US6297352 Washing solution comprising water or a dilute solution of a water-soluble metal ion chelating agent; novolaks must contain low metal contaminants in advanced microlithographic electronic devices
10/02/2001US6297175 Depositing silicate glass on substrates, plasma enhanced vapor deposition
10/02/2001US6297174 Coating substrate surface with coating solution containing as film-forming solute uniformly dissolved in an organic solvent a nitrogen-containing organic compound to form coating layer, drying coating layer by evaporating, baking
10/02/2001US6297173 Process for forming a semiconductor device
10/02/2001US6297172 Method of forming oxide film
10/02/2001US6297171 Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride
10/02/2001US6297170 Sacrificial multilayer anti-reflective coating for mos gate formation
10/02/2001US6297168 Plasma etching a silicon dioxide layer, a masking layer with octacyclobutane with carbon tetrafluoride, difluoromethane, hexafluoroethane and oxygen
10/02/2001US6297167 In-situ etch of multiple layers during formation of local interconnects
10/02/2001US6297166 Method for modifying nested to isolated offsets
10/02/2001US6297165 Etching and cleaning methods
10/02/2001US6297163 Etching semiconductor with fluorocarbon of octafluorobutene, difluoromethane and carbon monoxide plasma gas, masking and dielectric layer
10/02/2001US6297162 Method to reduce silicon oxynitride etch rate in a silicon oxide dry etch
10/02/2001US6297161 Method for forming TFT array bus
10/02/2001US6297160 Application of pure aluminum to prevent pad corrosion
10/02/2001US6297159 Method and apparatus for chemical polishing using field responsive materials
10/02/2001US6297158 Stress management of barrier metal for resolving CU line corrosion
10/02/2001US6297157 Time ramped method for plating of high aspect ratio semiconductor vias and channels
10/02/2001US6297155 Method for forming a copper layer over a semiconductor wafer
10/02/2001US6297154 Process for semiconductor device fabrication having copper interconnects
10/02/2001US6297153 Method of manufacturing barrier metal film of semiconductor device and method of manufacturing metal interconnection film of semiconductor device using the same
10/02/2001US6297152 CVD process for DCS-based tungsten silicide
10/02/2001US6297151 Method and structure for manufacturing contact windows in semiconductor process
10/02/2001US6297150 Methods of manufacturing a semiconductor device with pores formed between and over wiring patterns of an interlevel insulating layer
10/02/2001US6297149 Methods for forming metal interconnects
10/02/2001US6297148 Method of forming a silicon bottom anti-reflective coating with reduced junction leakage during salicidation
10/02/2001US6297147 Plasma treatment for ex-situ contact fill
10/02/2001US6297146 Low resistivity semiconductor barrier layer manufacturing method
10/02/2001US6297145 Method of forming a wiring layer having an air bridge construction
10/02/2001US6297144 Damascene local interconnect process
10/02/2001US6297143 Process for forming a bit-line in a MONOS device
10/02/2001US6297142 Method for bonding a semiconductor chip to a lead-patterning substrate using a gold/tin alloy
10/02/2001US6297141 Mounting assembly of integrated circuit device and method for production thereof
10/02/2001US6297140 Method to plate C4 to copper stud
10/02/2001US6297139 Method of forming a contact hole in a semiconductor wafer
10/02/2001US6297138 Method of depositing a metal film onto MOS sensors
10/02/2001US6297137 Method for forming gate electrode in semiconductor device capable of preventing distortion of oxidation profile thereof
10/02/2001US6297136 Method for fabricating an embedded semiconductor device
10/02/2001US6297135 Method for forming silicide regions on an integrated device
10/02/2001US6297133 Method of fabricating well
10/02/2001US6297132 Process to control the lateral doping profile of an implanted channel region
10/02/2001US6297131 Semiconductor device manufacturing method for grinding and dicing a wafer from a back side of the wafer
10/02/2001US6297130 Recessed, sidewall-sealed and sandwiched poly-buffered LOCOS isolation methods
10/02/2001US6297128 Process for manufacturing shallow trenches filled with dielectric material having low mechanical stress
10/02/2001US6297127 Self-aligned deep trench isolation to shallow trench isolation
10/02/2001US6297126 Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts
10/02/2001US6297125 Air-bridge integration scheme for reducing interconnect delay
10/02/2001US6297123 Method of preventing neck oxidation of a storage node
10/02/2001US6297122 Forming a conductive film of alkaline earth ruo3, vapor deposition and beta diketone complexes of ruthenium
10/02/2001US6297121 Fabrication method for capacitors in integrated circuits with a self-aligned contact structure
10/02/2001US6297120 Method of manufacturing a semiconductor device
10/02/2001US6297119 Semiconductor device and its manufacture
10/02/2001US6297118 Vertical bipolar semiconductor power transistor with an interdigitzed geometry, with optimization of the base-to-emitter potential difference
10/02/2001US6297117 Formation of confined halo regions in field effect transistor
10/02/2001US6297116 Method for manufacturing a metal oxide semiconductor (MOS)-based structure
10/02/2001US6297115 Cmos processs with low thermal budget
10/02/2001US6297114 Semiconductor device and process and apparatus of fabricating the same
10/02/2001US6297113 Method of manufacturing a semiconductor device, and a semiconductor device manufactured thereby
10/02/2001US6297112 Method of forming a MOS transistor
10/02/2001US6297111 Self-aligned channel transistor and method for making same
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