Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
02/2002
02/14/2002WO2002012948A2 Pneumatic control system and method for shaping deformable mirrors in lithographic projection systems
02/14/2002WO2002012928A2 Diffraction spectral filter for use in extreme-uv lithography condenser
02/14/2002WO2002012871A1 X-ray measuring and testing system
02/14/2002WO2002012870A2 System and method for inspecting bumped wafers
02/14/2002WO2002012780A1 Automatic refill system for ultra pure or contamination sensitive chemicals
02/14/2002WO2002012598A1 Epitaxial wafer apparatus
02/14/2002WO2002012589A2 Barrier layer structure for copper metallization and method of forming the structure
02/14/2002WO2002012588A1 Gas collector for epitaxial reactor
02/14/2002WO2002012587A2 Processing apparatus and cleaning method
02/14/2002WO2002012585A2 Processing apparatus and cleaning method
02/14/2002WO2002012350A2 Photoinitiated reactions
02/14/2002WO2002012115A2 Methods for reducing the curvature in boron-doped silicon micromachined structures
02/14/2002WO2002012098A1 Detection and handling of semiconductor wafers and wafer-like objects
02/14/2002WO2002012097A1 Handler for transporting flat substrates used in the semiconductor industry
02/14/2002WO2002012066A1 Device and method for the placement of components on transport belts
02/14/2002WO2002011966A1 Mold cleaning sheet and method of producing semiconductor devices using the same
02/14/2002WO2002011947A2 Method for processing a semiconductor wafer using double-side polishing
02/14/2002WO2002011911A1 Inverted pressure vessel with shielded closure mechanism
02/14/2002WO2002011858A1 Fluid media particle isolating system
02/14/2002WO2001078132A3 Method for transferring semiconductor device layers to different substrates
02/14/2002WO2001073820A3 Flow control of process gas in semiconductor manufacturing
02/14/2002WO2001067500A3 Methods for making nearly planar dielectric films in integrated circuits
02/14/2002WO2001067495A3 Semiconductor trenches and formation thereof
02/14/2002WO2001066832A3 Graded thin films
02/14/2002WO2001065606A3 Field effect transistor configuration having a high latch-up strength and method for the production thereof
02/14/2002WO2001065600A3 Nanoscale patterning for the formation of extensive wires
02/14/2002WO2001058765A3 Method and apparatus of immobilizing solder spheres
02/14/2002WO2001056076A8 An integrated circuit with shallow trench isolation and fabrication process
02/14/2002WO2001045175A3 Self-aligned ldd formation with one-step implantation for transistor formation
02/14/2002WO2001045151A3 Thin-film resistor with high temperature coefficient for use as passive semiconductor component for integrated circuits, and method for producing the same
02/14/2002WO2001044540A3 Method and device for monitoring etching chambers
02/14/2002WO2001043174A3 Fabrication of gallium nitride layers on textured silicon substrates
02/14/2002WO2001040884A3 Monitoring system for a conveying device that conveys flat articles, especially wafers
02/14/2002WO2001005197A3 High-speed symmetrical plasma treatment system
02/14/2002WO2000065301A9 Helium-neon laser light source generating two harmonically related, single-frequency wavelengths for use in displacement and dispersion measuring interferometry
02/14/2002WO2000034985A3 Method for structuring a metalliferous layer
02/14/2002US20020019968 Method and apparatus for verifying mask pattern data according to given rules
02/14/2002US20020019729 Visual inspection and verification system
02/14/2002US20020019454 Ultraviolet-curable pressure sensitive adhesive composition and ultraviolet- curable pressure sensitive adhesive sheet
02/14/2002US20020019204 Precise polishing apparatus and method
02/14/2002US20020019202 Control of removal rates in CMP
02/14/2002US20020019198 Polishing method and apparatus, and device fabrication method
02/14/2002US20020019197 Method and apparatus for controlling pH during planarization and cleaning of microelectronic substrates
02/14/2002US20020019194 Method and apparatus for wireless transfer of chemical-mechanical planarization measurements
02/14/2002US20020019152 Microelectric contact structure
02/14/2002US20020019149 Process for manufacturing semiconductor integrated circuit device including treatment of gas used in the process
02/14/2002US20020019148 Thermally induced reflectivity switch for laser thermal processing
02/14/2002US20020019147 Plasma CVD method
02/14/2002US20020019146 Semiconductor device and production thereof
02/14/2002US20020019145 Deposition of nanoporous silica films using a closed cup coater
02/14/2002US20020019144 Method of forming silicon oxide layer and method of manufacturing thin film transistor thereby
02/14/2002US20020019143 Farication of high quality oxides by controlling spacing between semiconductor wafers during processing
02/14/2002US20020019142 Methods of forming transistors associated with semiconductor substrates
02/14/2002US20020019140 Method of controlling striations and CD loss in contact oxide etch
02/14/2002US20020019139 Method and apparatus for etch passivating and etching a substrate
02/14/2002US20020019138 Method for removing structures
02/14/2002US20020019136 Method of manufacturing optical element
02/14/2002US20020019135 Method for reducing dishing effects during a chemical mechanical polishing process
02/14/2002US20020019134 Method and apparatus for manufacturing semiconductor device
02/14/2002US20020019133 Resin for semiconductor wire
02/14/2002US20020019131 Manufacture of semiconductor device with copper wiring
02/14/2002US20020019130 Process for fabricating semiconductor device, apparatus using more than one kind of inert gas for evacuating air and method for entering wafer into the apparatus
02/14/2002US20020019129 Semiconductor device and method of manufacturing the same
02/14/2002US20020019128 Slurry for chemical mechanical polishing of metal layer, method of preparing the slurry, and metallization method using the slurry
02/14/2002US20020019127 Interconnect structure and method of making
02/14/2002US20020019126 Self-aligned etch stop for polycrystalline silicon plugs on a semiconductor device
02/14/2002US20020019125 Methods of forming materials between conductive electrical components, and insulating materials
02/14/2002US20020019124 Semiconductor integrated circuit device and method for making the same
02/14/2002US20020019123 Copper MIM structure and process for mixed-signal and Rf capacitors and inductors
02/14/2002US20020019121 Method of forming a metal wiring in a semiconductor device
02/14/2002US20020019120 Methods of forming semiconductor structures
02/14/2002US20020019119 HIgh temperature metal deposition for reducing lateral silicidation
02/14/2002US20020019118 Method for non mass selected ion implant profile control
02/14/2002US20020019117 Forming silicon layer, doping, and carbonization after formation of doped silicon substance; use as semiconductor device
02/14/2002US20020019116 To deposit a multi-component layer on a semiconductor substrate; for example a dielectric layer from a gaseous titanium organometallic precursor, reactive silane-based gas and gaseous oxidant
02/14/2002US20020019115 Power rectifier device and method of fabricating power rectifier devices
02/14/2002US20020019114 Methods of forming integrated circuitry.
02/14/2002US20020019113 Method for self-aligned shallow trench isolation and method of manufacturing non-volatile memory device comprising the same
02/14/2002US20020019112 Low dielectric constant shallow trench isolation
02/14/2002US20020019111 Semiconductor with high-voltage components and low-voltage components on a shared die
02/14/2002US20020019110 Method of fabricating capacitors for semiconductor devices
02/14/2002US20020019109 Semiconductor memory device production method
02/14/2002US20020019108 Crystallization temperature of a ferroelectric layer such as strontium bismuth tantalate (SBT) dielectric is lowered by applying a thin cerium oxide (CeO2) layer to a first electrode layer before the ferroelectric layer is deposited
02/14/2002US20020019107 Adhesion force between the rare metal layer electrode and insulating layer is increased; random access memory (DRAM)
02/14/2002US20020019106 Methods of forming capacitors
02/14/2002US20020019105 SOI substrate and semiconductor device
02/14/2002US20020019104 Method of manufacturing semiconductor device and semiconductor integrated circuit device
02/14/2002US20020019103 Tilt-angle ion implant to improve junction breakdown in flash memory application
02/14/2002US20020019102 Process to fabricate a novel source-drain extension
02/14/2002US20020019101 Semiconductor device and method for fabricating the same
02/14/2002US20020019100 Method for manufacturing semiconductor integrated circuit device having deposited layer for gate insulation
02/14/2002US20020019099 Super self-aligned trench-gate dmos with reduced on-resistance
02/14/2002US20020019098 Having a floating gate and a control gate laterally spaced apart, and both insulated from a substrate
02/14/2002US20020019097 Nonvolatile semiconductor memory device and method for fabricating the device
02/14/2002US20020019096 Silicon on insulator transistor structure for imbedded DRAM
02/14/2002US20020019095 Semiconductor device incorporating an electrical contact to an internal conductive layer and method for making the same
02/14/2002US20020019094 Method of forming a storage node of a capacitor that prevents HSG bridging
02/14/2002US20020019093 Barium strontium titanate, (Sr,Ba)TiO3 (BST) by supplying BST sources into a chamber; and inducing textured growth of the film over the substrate in a uniform desired crystal orientation; metal-organic chemical vapor deposition (MOCVD)
02/14/2002US20020019092 Method for manufacturing semiconductor device having uniform silicon glass film
02/14/2002US20020019091 Method for the fabrication of semiconductor device