| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 02/26/2002 | US6350704 Heating, drying and/or pyrolyzing oxide and carbon sources; transforming into porous glass dielectric |
| 02/26/2002 | US6350703 Semiconductor substrate and production method thereof |
| 02/26/2002 | US6350702 Fabrication process of semiconductor substrate |
| 02/26/2002 | US6350701 Etching system |
| 02/26/2002 | US6350700 Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure |
| 02/26/2002 | US6350699 Method for anisotropic plasma etching using non-chlorofluorocarbon, fluorine-based chemistry |
| 02/26/2002 | US6350698 Dry etching apparatus and its manufacturing method |
| 02/26/2002 | US6350697 Method of cleaning and conditioning plasma reaction chamber |
| 02/26/2002 | US6350696 Spacer etch method for semiconductor device |
| 02/26/2002 | US6350695 Pillar process for copper interconnect scheme |
| 02/26/2002 | US6350694 Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials |
| 02/26/2002 | US6350693 Method of CMP of polysilicon |
| 02/26/2002 | US6350692 Dispensing inorganic fluorine compound on surface in solution |
| 02/26/2002 | US6350690 Process for achieving full global planarization during CMP of damascene semiconductor structures |
| 02/26/2002 | US6350689 Complexing oxidizing radical with vaporized chelate compound; dry cleaning reduces cross-contamination |
| 02/26/2002 | US6350688 Annealing deposited metal layer on semiconductor substrate in vacuum; planarization; reducing via resistance via interconnects; |
| 02/26/2002 | US6350687 Treating copper or its alloy surface with corrosion inhibitor compound; electroless plating metal on surface; vapor deposition of metal; capping with nitride |
| 02/26/2002 | US6350686 Vapor deposition multi-metallic mixture of metalloamides; alloying, boriding, siliciding, oxidation, nitriding, and/or sulfiding; controlled stoichiometry; semiconductors |
| 02/26/2002 | US6350685 Method for manufacturing semiconductor devices |
| 02/26/2002 | US6350684 Graded/stepped silicide process to improve MOS transistor |
| 02/26/2002 | US6350683 Method of forming a tungsten plug in a hole |
| 02/26/2002 | US6350682 Method of fabricating dual damascene structure using a hard mask |
| 02/26/2002 | US6350681 Method of forming dual damascene structure |
| 02/26/2002 | US6350680 Pad alignment for AlCu pad for copper process |
| 02/26/2002 | US6350679 Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry |
| 02/26/2002 | US6350678 Chemical-mechanical polishing of semiconductors |
| 02/26/2002 | US6350677 Method for forming a self-aligned silicide layer |
| 02/26/2002 | US6350676 Method of forming high-stability metallic contacts in an integrated circuit with one or more metallized layers |
| 02/26/2002 | US6350675 Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects |
| 02/26/2002 | US6350674 Manufacturing method for semiconductor device having a multilayer interconnect |
| 02/26/2002 | US6350673 Method for decreasing CHC degradation |
| 02/26/2002 | US6350672 Interconnect structure with gas dielectric compatible with unlanded vias |
| 02/26/2002 | US6350671 Method for autoaligning overlapped lines of a conductive material in integrated electronic circuits |
| 02/26/2002 | US6350670 Method for making a semiconductor device having a carbon doped oxide insulating layer |
| 02/26/2002 | US6350669 Method of bonding ball grid array package to circuit board without causing package collapse |
| 02/26/2002 | US6350667 Method of improving pad metal adhesion |
| 02/26/2002 | US6350666 Method and apparatus for producing group-III nitrides |
| 02/26/2002 | US6350665 Semiconductor structure and method of making contacts and source and/or drain junctions in a semiconductor device |
| 02/26/2002 | US6350664 Semiconductor device and method of manufacturing the same |
| 02/26/2002 | US6350663 Method for reducing leakage currents of active area diodes and source/drain diffusions |
| 02/26/2002 | US6350662 Method to reduce defects in shallow trench isolations by post liner anneal |
| 02/26/2002 | US6350661 Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts |
| 02/26/2002 | US6350660 Process for forming a shallow trench isolation |
| 02/26/2002 | US6350659 Process of making semiconductor device having regions of insulating material formed in a semiconductor substrate |
| 02/26/2002 | US6350657 Inexpensive method of manufacturing an SOI wafer |
| 02/26/2002 | US6350656 SEG combined with tilt side implant process |
| 02/26/2002 | US6350655 Semiconductor device and a method of manufacturing the same |
| 02/26/2002 | US6350654 Semiconductor read-only memory device and method of fabricating the same |
| 02/26/2002 | US6350653 Embedded DRAM on silicon-on-insulator substrate |
| 02/26/2002 | US6350652 Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions |
| 02/26/2002 | US6350651 Method for making flash memory with UV opaque passivation layer |
| 02/26/2002 | US6350650 Method for fabricating a semiconductor memory device |
| 02/26/2002 | US6350649 Bit line landing pad and borderless contact on bit line stud with etch stop layer and manufacturing method thereof |
| 02/26/2002 | US6350648 Formation of conductive rugged silicon |
| 02/26/2002 | US6350647 Semiconductor memory device and manufacturing method of the same |
| 02/26/2002 | US6350646 Method for reducing thermal budget in node contact application |
| 02/26/2002 | US6350644 Ferroelectric thin-film device and method for producing the same |
| 02/26/2002 | US6350643 Vapor deposition; annealing to ferroelectric layer; semiconductors, integrated circuits |
| 02/26/2002 | US6350642 Method of manufacturing semiconductor memory device including various contact studs |
| 02/26/2002 | US6350641 Method of increasing the depth of lightly doping in a high voltage device |
| 02/26/2002 | US6350639 Simplified graded LDD transistor using controlled polysilicon gate profile |
| 02/26/2002 | US6350638 Method of forming complementary type conductive regions on a substrate |
| 02/26/2002 | US6350637 Method of fabrication of a no-field MOS transistor |
| 02/26/2002 | US6350635 Memory cell having a vertical transistor with buried source/drain and dual gates |
| 02/26/2002 | US6350633 Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint |
| 02/26/2002 | US6350632 Semiconductor chip assembly with ball bond connection joint |
| 02/26/2002 | US6350631 Electronic device, method of manufacturing the same, and apparatus for manufacturing the same |
| 02/26/2002 | US6350628 Method of fabricating a field emission device on the sidewalls of holes formed in an insulator layer |
| 02/26/2002 | US6350627 Interlevel dielectric thickness monitor for complex semiconductor chips |
| 02/26/2002 | US6350625 Optoelectronic packaging submount arrangement providing 90 degree electrical conductor turns and method of forming thereof |
| 02/26/2002 | US6350623 Method of forming intermediate structures in porous substrates in which electrical and optical microdevices are fabricated and intermediate structures formed by the same |
| 02/26/2002 | US6350560 Rinse composition |
| 02/26/2002 | US6350559 Method for creating thinner resist coating that also has fewer pinholes |
| 02/26/2002 | US6350549 Jig for producing pellicle and method for producing pellicle using the same |
| 02/26/2002 | US6350547 Oxide structure having a finely calibrated thickness |
| 02/26/2002 | US6350497 Plasma processing method |
| 02/26/2002 | US6350494 Controlling drops of metal, raster scanning and blanking |
| 02/26/2002 | US6350489 Deposited-film forming process and deposited-film forming apparatus |
| 02/26/2002 | US6350425 Bubbling pure ammonia and hydrogen fluoride |
| 02/26/2002 | US6350393 Use of CsOH in a dielectric CMP slurry |
| 02/26/2002 | US6350391 Laser stripping improvement by modified gas composition |
| 02/26/2002 | US6350390 Plasma etch method for forming patterned layer with enhanced critical dimension (CD) control |
| 02/26/2002 | US6350386 Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly |
| 02/26/2002 | US6350365 Method of producing multilayer circuit board |
| 02/26/2002 | US6350364 Method for improvement of planarity of electroplated copper |
| 02/26/2002 | US6350353 Apparatus comprising processing chamber, substrate support member disposed in the processing chamber having first power source coupled thereto, target disposed in the processing chamber, second power source, electromagnetic field source |
| 02/26/2002 | US6350334 Method of manufacturing a multi-layered ceramic substrate |
| 02/26/2002 | US6350322 Method of reducing water spotting and oxide growth on a semiconductor structure |
| 02/26/2002 | US6350321 UHV horizontal hot wall cluster CVD/growth design |
| 02/26/2002 | US6350320 Heater for processing chamber |
| 02/26/2002 | US6350319 Micro-environment reactor for processing a workpiece |
| 02/26/2002 | US6350317 Linear drive system for use in a plasma processing system |
| 02/26/2002 | US6350315 Methods of producing doped semiconductors |
| 02/26/2002 | US6350314 Process for producing nitrogen-doped semiconductor wafers |
| 02/26/2002 | US6350311 Method for forming an epitaxial silicon-germanium layer |
| 02/26/2002 | US6350188 Drive system for a carrier head support structure |
| 02/26/2002 | US6350186 Apparatus and method for chemical mechanical polishing |
| 02/26/2002 | US6350184 Polishing pad conditioning device with cutting elements |
| 02/26/2002 | US6350179 Method for determining a polishing recipe based upon the measured pre-polish thickness of a process layer |
| 02/26/2002 | US6350177 Combined CMP and wafer cleaning apparatus and associated methods |