| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 03/12/2002 | US6356089 Contact probe arrangement |
| 03/12/2002 | US6355994 Precision stage |
| 03/12/2002 | US6355985 Integrated circuit device and synchronous-link dynamic random access memory device |
| 03/12/2002 | US6355984 Input-output circuit cell and semiconductor integrated circuit apparatus |
| 03/12/2002 | US6355983 Surface modified interconnects |
| 03/12/2002 | US6355982 Semiconductor memory device having pairs of bit lines arranged on both sides of memory cells |
| 03/12/2002 | US6355979 Hard mask for copper plasma etch |
| 03/12/2002 | US6355975 Semiconductor device and manufacturing method thereof |
| 03/12/2002 | US6355974 Method to prevent the formation of a thinner portion of insulating layer at the junction between the side walls and the bottom insulator |
| 03/12/2002 | US6355973 Integrated circuit having a sealed edge |
| 03/12/2002 | US6355972 Semiconductor device and method of manufacturing same |
| 03/12/2002 | US6355971 Semiconductor switch devices having a region with three distinct zones and their manufacture |
| 03/12/2002 | US6355970 Semiconductor device having a high frequency electronic circuit |
| 03/12/2002 | US6355969 Programmable integrated circuit structures and methods for making the same |
| 03/12/2002 | US6355967 Semiconductor device and method of manufacturing the same |
| 03/12/2002 | US6355966 Trench isolation region comprising a material selected from the group consisting of a silicon oxynitride, al2o3 or ta2o5; received at least partially within the semiconductor substrate proximate the trench isolation region. |
| 03/12/2002 | US6355963 MOS type semiconductor device having an impurity diffusion layer |
| 03/12/2002 | US6355962 CMOS FET with P-well with P- type halo under drain and counterdoped N- halo under source region |
| 03/12/2002 | US6355956 Thin film transistor for protecting source and drain metal lines |
| 03/12/2002 | US6355955 Transistor and a method for forming the transistor with elevated and/or relatively shallow source/drain regions to achieve enhanced gate electrode formation |
| 03/12/2002 | US6355954 Device with asymmetrical channel dopant profile |
| 03/12/2002 | US6355952 Capacitor having ferroelectric film and multiple layers of insulating and protective films for nonvolatile memory cell |
| 03/12/2002 | US6355951 Field effect semiconductor device |
| 03/12/2002 | US6355950 Substrate interconnect for power distribution on integrated circuits |
| 03/12/2002 | US6355948 Semiconductor integrated circuit device |
| 03/12/2002 | US6355947 Heterojunction bipolar transistor with band gap graded emitter |
| 03/12/2002 | US6355945 Gaas substrate; preferably a light-emitting/light-receiving layer including a gan-based compound |
| 03/12/2002 | US6355944 Silicon carbide LMOSFET with gate reach-through protection |
| 03/12/2002 | US6355943 Thin film transistor, method of producing the same, liquid crystal display, and thin film forming apparatus |
| 03/12/2002 | US6355941 Semiconductor device |
| 03/12/2002 | US6355909 Method and apparatus for thermal processing of semiconductor substrates |
| 03/12/2002 | US6355902 Plasma film forming method and plasma film forming apparatus |
| 03/12/2002 | US6355874 Semiconductor device and solar cell |
| 03/12/2002 | US6355750 Curable adhesive comprising siloxane-containing maleimide compound and free radical- or photoinitiator; semiconductors, integrated circuits |
| 03/12/2002 | US6355716 Antistatic agents; heat resistance |
| 03/12/2002 | US6355582 Silicon nitride film formation method |
| 03/12/2002 | US6355581 Placing substrate having stepped upper surface in reaction chamber, inducing reaction in gaseous mixture comprising silicon and oxygen sources, carrier gas and halide-containing inorganic gas additive to deposit silicon oxide film |
| 03/12/2002 | US6355580 Bombarding oxygen atoms proximate silicon dioxide region with at least one inert ion in atmosphere consisting essentially of inert ion and at least one oxidant to energize oxygen atoms proximate region and to increase thickness of silicon oxide |
| 03/12/2002 | US6355579 Method for forming gate oxide film in semiconductor device |
| 03/12/2002 | US6355577 System to reduce particulate contamination |
| 03/12/2002 | US6355576 Treating circuit with carbon tetrafluoride, water vapor and nitrogen to volatilize fluorine from metal contact and soften metallic polymers adhering to sidewalls of opening, ashing to remove resist, stripping in solvent to remove impurities |
| 03/12/2002 | US6355575 Depositing layer comprising hydrogen silsesquioxane on conductive pattern, forming two dielectric layers, forming photoresist mask on second dielectric layer, etching to form opening exposing first dielectric layer, removing photoresist |
| 03/12/2002 | US6355574 Method and device for treating a semiconductor surface |
| 03/12/2002 | US6355573 Plasma processing method and apparatus |
| 03/12/2002 | US6355572 Etching contact holes in insulating film composed of organic spin on glass using resist pattern formed over insulating layer as mask, removing resist pattern by plasma treatment in gas mixture of oxygen and diimide |
| 03/12/2002 | US6355571 Method and apparatus for reducing copper oxidation and contamination in a semiconductor device |
| 03/12/2002 | US6355569 Dry etching method and apparatus |
| 03/12/2002 | US6355568 Cleaning method for copper dual damascene process |
| 03/12/2002 | US6355567 Retrograde openings in thin films |
| 03/12/2002 | US6355566 Method of removing surface defects or other recesses during the formation of a semiconductor device |
| 03/12/2002 | US6355565 Chemical-mechanical-polishing slurry and method for polishing metal/oxide layers |
| 03/12/2002 | US6355564 Selectively etching bulk silicon in target region in back side of semiconductor using reactive ion etching gas comprising sulfur hexafluoride and nitrogen and using epitaxial silicon as endpoint indicator, accessing circuitry via exposed region |
| 03/12/2002 | US6355563 Versatile copper-wiring layout design with low-k dielectric integration |
| 03/12/2002 | US6355562 Adhesion promotion method for CVD copper metallization in IC applications |
| 03/12/2002 | US6355561 ALD method to improve surface coverage |
| 03/12/2002 | US6355560 Sputtering titanium layer over surfaces of aperture, chemical vapor depositing titanium nitride over titanium layer, each layer having specified thickness, depositing metal over titanium nitride |
| 03/12/2002 | US6355559 Forming transition metal over metal interconnect line on semiconductor, annealing to react portion with interconnect line to form self-aligned metal compound, removing unreacted transition metal, annealing in nitrogen to form nitride |
| 03/12/2002 | US6355558 Metallization structure, and associated method, to improve crystallographic texture and cavity fill for CVD aluminum/PVD aluminum alloy films |
| 03/12/2002 | US6355557 Oxide plasma etching process with a controlled wineglass shape |
| 03/12/2002 | US6355556 Method for fabricating transistor |
| 03/12/2002 | US6355555 Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer |
| 03/12/2002 | US6355554 Methods of forming filled interconnections in microelectronic devices |
| 03/12/2002 | US6355553 Method of forming a metal plug in a contact hole |
| 03/12/2002 | US6355552 Integrated circuit with stop layer and associated fabrication process |
| 03/12/2002 | US6355551 Integrated circuit having a void between adjacent conductive lines |
| 03/12/2002 | US6355550 Ultra-late programming ROM and method of manufacture |
| 03/12/2002 | US6355549 Method of forming polycide structures |
| 03/12/2002 | US6355548 Forming aluminum nitride layer on semiconductor substrate, annealing to convert aluminum nitride into aluminum oxide, forming conductive layer on aluminum oxide layer, patterning conductive layer and aluminum oxide layer into gate structure |
| 03/12/2002 | US6355547 Method of forming a self-aligned contact pad for a semiconductor device |
| 03/12/2002 | US6355546 Thermally grown protective oxide buffer layer for ARC removal |
| 03/12/2002 | US6355545 Method and apparatus for wiring, wire, and integrated circuit |
| 03/12/2002 | US6355544 Selective high concentration doping of semiconductor material utilizing laser annealing |
| 03/12/2002 | US6355543 Laser annealing for forming shallow source/drain extension for MOS transistor |
| 03/12/2002 | US6355542 Semiconductor device and manufacturing method |
| 03/12/2002 | US6355541 Method for transfer of thin-film of silicon carbide via implantation and wafer bonding |
| 03/12/2002 | US6355540 Stress-free shallow trench isolation |
| 03/12/2002 | US6355539 Method for forming shallow trench isolation |
| 03/12/2002 | US6355538 Method of forming isolation material with edge extension structure |
| 03/12/2002 | US6355537 Method of providing radio frequency isolation of device mesas using guard ring regions within an integrated circuit device |
| 03/12/2002 | US6355536 Selective method to form roughened silicon |
| 03/12/2002 | US6355535 Method and structure of manufacturing a high-Q inductor with an air trench |
| 03/12/2002 | US6355533 Method for manufacturing semiconductor device |
| 03/12/2002 | US6355532 Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET |
| 03/12/2002 | US6355531 Method for fabricating semiconductor devices with different properties using maskless process |
| 03/12/2002 | US6355530 Method of manufacturing a mask ROM bit line |
| 03/12/2002 | US6355529 Method of fabricating memory cell with vertical transistor |
| 03/12/2002 | US6355528 Method to form narrow structure using double-damascene process |
| 03/12/2002 | US6355527 Method to increase coupling ratio of source to floating gate in split-gate flash |
| 03/12/2002 | US6355526 Non-volatile semiconductor memory device and method of manufacturing the same |
| 03/12/2002 | US6355525 Method of producing non-volatile semiconductor memory device having a floating gate with protruding conductive side-wall portions |
| 03/12/2002 | US6355524 Nonvolatile memory structures and fabrication methods |
| 03/12/2002 | US6355523 Manufacturing process for making single polysilicon level flash EEPROM cell |
| 03/12/2002 | US6355522 Effect of doped amorphous Si thickness on better poly 1 contact resistance performance for nand type flash memory devices |
| 03/12/2002 | US6355521 Method of manufacturing a capacitor in a semiconductor device |
| 03/12/2002 | US6355520 Method for fabricating 4F2 memory cells with improved gate conductor structure |
| 03/12/2002 | US6355519 Method for fabricating capacitor of semiconductor device |
| 03/12/2002 | US6355518 Method for making a DRAM cell with deep-trench capacitors and overlying vertical transistors |
| 03/12/2002 | US6355517 Method for fabricating semiconductor memory with a groove |
| 03/12/2002 | US6355516 Forming polysilicon film on semiconductor substrate, forming buffer layer and metal layer on film to form lower electrode and tantalum pentoxide film on metal layer, performing plasma process in mixture of nitrogen and oxygen to reduce impurities |
| 03/12/2002 | US6355515 Wiring structure of semiconductor device and method for manufacturing the same |