Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2002
03/07/2002WO2002019380A1 Plasma processing
03/07/2002WO2002019378A2 System and method for removing particles entrained in an ion beam
03/07/2002WO2002019377A2 Electrostatic trap for particles entrained in an ion beam
03/07/2002WO2002019376A2 System and method for removing contaminant particles relative to an ion beam
03/07/2002WO2002019375A1 Device, set and method for carrying a gas or a liquid to a surface through a tube
03/07/2002WO2002019374A2 Methods and apparatus for adjusting beam parallelism in ion implanters
03/07/2002WO2002019363A2 Pre-polycoating of glass substrates
03/07/2002WO2002019338A1 Memory cell arrangement and method for the production thereof
03/07/2002WO2002019337A2 Mtj mram series-parallel architecture
03/07/2002WO2002019336A2 Mtj mram parallel-parallel architecture
03/07/2002WO2002019112A1 Fuse configurations for low-voltage flash memories
03/07/2002WO2002019036A1 Fabrication of nanoelectronic circuits
03/07/2002WO2002019033A2 Photoacid generators and photoresists comprising same
03/07/2002WO2002018960A2 Device and method for characterizing the version of integrated circuits and use for controlling operations
03/07/2002WO2002018871A1 Improved overlay alignment measurement mark
03/07/2002WO2002018680A1 Device and method for the deposition of, in particular, crystalline layers on, in particular, crystalline substrates
03/07/2002WO2002018672A1 Cvd coating device
03/07/2002WO2002018670A2 Cvd reactor with a gas outlet ring made of solid graphite
03/07/2002WO2002018653A2 Method for depositing nitride layers
03/07/2002WO2002018266A1 Single molecule array on silicon substrate for quantum computer
03/07/2002WO2002018220A1 Packaging bag for semiconductor wafer and method of packaging semiconductor wafer using the packaging bag
03/07/2002WO2002018107A1 Edge grip aligner with buffering capabilities
03/07/2002WO2002018101A2 Chemical mechanical polishing (cmp) head, apparatus, and method and planarized semiconductor wafer produced thereby
03/07/2002WO2002018100A2 Method and apparatus for measuring a polishing condition
03/07/2002WO2002018099A2 Slurry for use with fixed-abrasive polishing pads in polishing semiconductor device conductive structures that include copper and tungsten and polishing methods
03/07/2002WO2002018080A1 Metal colloidal solution composition and conductor or ink for forming semiconductor pattern comprising it and method for forming conductor or semiconductor pattern
03/07/2002WO2001097282B1 Method for making substrates and resulting substrates
03/07/2002WO2001094656A3 Plating apparatus with individually controllable anode segments and associated method
03/07/2002WO2001093312A3 Method for depositing a selected thickness of an interlevel dielectric material to achieve optimum global planarity on a semiconductor wafer
03/07/2002WO2001089763A3 Multilayer retaining ring for chemical mechanical polishing
03/07/2002WO2001088955A3 Method of monitoring ion implants by examination of an overlying masking material
03/07/2002WO2001078110A3 Low dielectric constant organic dielectrics based on cage-like structures
03/07/2002WO2001073841A3 Method of preventing bridging between polycrystalline micro-scale features
03/07/2002WO2001073822A3 Visibly marked parts and method for using same
03/07/2002WO2001072430A3 Drip manifold for uniform chemical delivery
03/07/2002WO2001071800A3 Method for forming a silicide gate stack for use in a self-aligned contact etch
03/07/2002WO2001069676A3 Method and apparatus for bonding substrates
03/07/2002WO2001063362A3 Resist materials for 157-nm lithography
03/07/2002WO2001061750A3 Method of etching a shaped cavity
03/07/2002WO2001059850A3 Structures and methods for improved capacitor cells
03/07/2002WO2001054002A8 System and method for h-tree clocking layout
03/07/2002WO2001052311A3 Method of preparing a semiconductor substrate for subsequent silicide formation
03/07/2002WO2001050510A3 Low thermal budget metal oxide deposition for capacitor structures
03/07/2002WO2001048819A3 Interconnect structure and method of fabrication therefor
03/07/2002WO2001042163A3 High-purity low-resistivity electrostatic chucks
03/07/2002US20020029373 Semiconductor memory device and method for manufacturing the same
03/07/2002US20020029372 Method for fabricating a full depletion type SOI device
03/07/2002US20020029124 Method for testing a CMOS integrated circuit
03/07/2002US20020029118 Sampling inspection managing system
03/07/2002US20020029093 Method and apparatus for depositing a tantalum-containing layer on a substrate
03/07/2002US20020028646 Chemical mechanical planarization or polishing pad with sections having varied groove patterns
03/07/2002US20020028641 Probe end cleaning sheet
03/07/2002US20020028640 Method and apparatus for cleaning a surface of a microelectronic substrate
03/07/2002US20020028639 Aqueous solution for colloidal polishing of silicate substrates
03/07/2002US20020028636 Polishing composition
03/07/2002US20020028632 Polishing composition and manufacturing and polishing methods
03/07/2002US20020028629 Method and apparatus for wireless transfer of chemical-mechanical planarization measurements
03/07/2002US20020028599 Methods employing hybrid adhesive materials to secure components of semiconductor device assemblies and packages to one another and assemblies and packages including components secured to one another with such hybrid adhesive materials
03/07/2002US20020028596 Mounting pin and mounting device
03/07/2002US20020028595 Method for assembling integral type electronic component and integral type electronic component
03/07/2002US20020028587 Method of manufacturing interlayer dielectric film using vacuum ultraviolet CVD
03/07/2002US20020028586 Mixture of water and terafluoromethane vapors
03/07/2002US20020028585 Containing hydrogen peroxide, chelate compound, hydrogen and fluorine gases
03/07/2002US20020028584 Covering wires with dielectrics
03/07/2002US20020028583 Method and system for etching tunnel oxide to reduce undercutting during memory array fabrication
03/07/2002US20020028582 Accuracy control of etching using plasma
03/07/2002US20020028581 Polishing with grindstone in liquid dispersant
03/07/2002US20020028580 Substrate polishing method
03/07/2002US20020028579 Low resistivity tantalum
03/07/2002US20020028578 Overcoating semiconductor; hydrogen reduction of tungsten hexafluoride
03/07/2002US20020028577 Method of forming a refractory metal silicide
03/07/2002US20020028576 Method and apparatus for forming improved metal interconnects
03/07/2002US20020028575 Method of manufacturing a semiconductor device
03/07/2002US20020028574 Semiconductor integrated circuit device having switching misfet and capacitor element and method of producing the same, including wiring therefor and method of producing such wiring
03/07/2002US20020028571 Transparent and conductive zinc oxide film with low growth temperature
03/07/2002US20020028570 Control stoichiometry
03/07/2002US20020028569 Semiconductor device and method of manufacturing same
03/07/2002US20020028568 Semiconductor device and method of manufacturing same
03/07/2002US20020028567 Film formation method and film formation apparatus
03/07/2002US20020028566 CVD film formation method
03/07/2002US20020028565 Method for growing p-type III-V compound material utilizing HVPE techniques
03/07/2002US20020028564 Method of producing a single crystal gallium nitride substrate and single crystal gallium nitride substrate
03/07/2002US20020028563 Methods of forming recessed hemispherical grain silicon capacitor structures
03/07/2002US20020028562 Method for fabricating a lower plate for a capacitor of semiconductor device
03/07/2002US20020028561 Semiconductor integrated circuit device and method of manufacturing the same
03/07/2002US20020028560 Semiconductor device and manufacturing method
03/07/2002US20020028559 Method and apparatus for providing low-GIDL dual workfunction gate doping with borderless diffusion contact
03/07/2002US20020028558 Method for forming gate electrode of MOS type transistor
03/07/2002US20020028556 RuSixOy-containing adhesion layers and process for fabricating the same
03/07/2002US20020028555 Mosfet with high dielectric constant gate insulator and minimum overlap capacitance
03/07/2002US20020028554 Formulation of multiple gate oxides thicknesses without exposing gate oxide or silicon surface to photoresist
03/07/2002US20020028553 Reduced fluctuations in retention time of stored charge
03/07/2002US20020028552 Positioning electrodes on dielectric substrate
03/07/2002US20020028551 Method for manufacturing semiconductor integrated circuit device
03/07/2002US20020028550 Semiconductor integrated circuit device and method of manufacturing the same, and cell size calculation method for DRAM memory cells
03/07/2002US20020028549 Ferroelectric randon access memory; high and low temperature annealing
03/07/2002US20020028548 Circuit and method of fabricating a memory cell for a static random access memory
03/07/2002US20020028547 Flash memory programming method
03/07/2002US20020028546 Method of fabricating deep submicron MOS transistor
03/07/2002US20020028545 Highly resistive static random access memory and method of fabricating the same
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