Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2002
03/19/2002US6359318 Semiconductor device with DMOS and bi-polar transistors
03/19/2002US6359317 Vertical PNP bipolar transistor and its method of fabrication
03/19/2002US6359316 Method and apparatus to prevent latch-up in CMOS devices
03/19/2002US6359313 Electrostatic discharge protection transistor for a semiconductor chip
03/19/2002US6359312 Semiconductor device with SOI structure
03/19/2002US6359311 Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same
03/19/2002US6359310 Shallow doped junctions with a variable profile gradation of dopants
03/19/2002US6359309 Power MOSFET and IGBT with optimized on-resistance and breakdown voltage
03/19/2002US6359307 Method for forming self-aligned contacts and interconnection lines using dual damascene techniques
03/19/2002US6359306 Semiconductor device and method of manufacturing thereof
03/19/2002US6359305 Trench-isolated EEPROM flash in segmented bit line page architecture
03/19/2002US6359304 Nonvolatile semiconductor memory and process for fabricating the same
03/19/2002US6359303 Split gate flash memory with virtual ground array structure and method of fabricating the same
03/19/2002US6359302 DRAM cells and integrated circuitry, and capacitor structures
03/19/2002US6359301 Semiconductor device and method of manufacturing the same
03/19/2002US6359300 High aspect ratio deep trench capacitor having void-free fill
03/19/2002US6359299 Apparatus and method for forming controlled deep trench top isolation layers
03/19/2002US6359298 Capacitively coupled DTMOS on SOI for multiple devices
03/19/2002US6359297 Semiconductor device with movement of positive ion prevented
03/19/2002US6359296 Circuit arrangement with at least one capacitor
03/19/2002US6359295 Ferroelectric memory devices including patterned conductive layers
03/19/2002US6359294 Insulator-compound semiconductor interface structure
03/19/2002US6359293 Integrated optoelectronic device with an avalanche photodetector and method of making the same using commercial CMOS processes
03/19/2002US6359290 Self-aligned bump bond infrared focal plane array architecture
03/19/2002US6359288 Nanowire arrays
03/19/2002US6359264 Thermal cycling module
03/19/2002US6359263 System for controlling the temperature of a reflective substrate during rapid heating
03/19/2002US6359255 Method for forming a through hole in a ceramic green sheet
03/19/2002US6359253 Unit-in-tray pocket checker
03/19/2002US6359250 RF matching network with distributed outputs
03/19/2002US6359236 Mounting component with leads having polymeric strips
03/19/2002US6359235 Electrical device mounting wiring board and method of producing the same
03/19/2002US6359221 Resin sealed semiconductor device, circuit member for use therein
03/19/2002US6359160 Bis(diethylamide)bis(tert-butylimido)molybdenum
03/19/2002US6359078 Resist materials for use in lithography, for example, in the production of integrated circuits
03/19/2002US6358867 Orientation independent oxidation of silicon
03/19/2002US6358866 Placing substrate in inert gaseous ambient in furnace, ambient having partial pressure within a predetermined range, ambient comprising molecules having suitable diameter for penetrating into silicon dioxide material, heating, cooling
03/19/2002US6358865 Oxidation of silicon using fluorine implant
03/19/2002US6358864 Silicon oxide and silicon nitride from low pressure chemical vapor deposition; one-reactor process for high throughput of memory devices; noncontaminating and noncracking of wafers
03/19/2002US6358863 Metal oxides and poly(para-xylylenes) for use in semiconductor devices; less interference (cross talk) and better reliability; improved thermal properties
03/19/2002US6358862 Passivation integrity improvements
03/19/2002US6358861 Manufacturing method of silicon device
03/19/2002US6358859 HBr silicon etching process
03/19/2002US6358857 Exposing insulative materials comprising complexes of metal and oxygen to etching conditions using oxygen-containing gas
03/19/2002US6358856 Bright field image reversal for contact hole patterning
03/19/2002US6358855 Clean method for recessed conductive barriers
03/19/2002US6358853 Abrasives
03/19/2002US6358852 Decapsulation techniques for multi-chip (MCP) devices
03/19/2002US6358850 Slurry-less chemical-mechanical polishing of oxide materials
03/19/2002US6358849 Integrated circuit interconnect and method
03/19/2002US6358848 Forming semiconductors of calcium copper alloy on copper
03/19/2002US6358847 Method for enabling conventional wire bonding to copper-based bond pad features
03/19/2002US6358846 Forming semiconductors with barriers
03/19/2002US6358845 Method for forming inter metal dielectric
03/19/2002US6358844 Tungsten deposition process with dual-step nucleation
03/19/2002US6358843 Method of making ultra small vias for integrated circuits
03/19/2002US6358842 Method to form damascene interconnects with sidewall passivation to protect organic dielectrics
03/19/2002US6358841 Method of copper CMP on low dielectric constant HSQ material
03/19/2002US6358840 Forming and filling a recess in interconnect with alloy to minimize electromigration
03/19/2002US6358839 Solution to black diamond film delamination problem
03/19/2002US6358838 Semiconductor device and process for producing the same
03/19/2002US6358837 Method of electrically connecting and isolating components with vertical elements extending between interconnect layers in an integrated circuit
03/19/2002US6358836 Wafer level package incorporating elastomeric pads in dummy plugs
03/19/2002US6358835 Method of manufacturing a semiconductor device
03/19/2002US6358834 Method of forming bumps on wafers or substrates
03/19/2002US6358833 Method of fabricating a micromachined chip scale package
03/19/2002US6358832 Method of forming barrier layers for damascene interconnects
03/19/2002US6358831 Method for forming a top interconnection level and bonding pads on an integrated circuit chip
03/19/2002US6358830 Method for manufacturing semiconductor device having interlayer dielectric film layers with like etch speeds
03/19/2002US6358829 Semiconductor device fabrication method using an interface control layer to improve a metal interconnection layer
03/19/2002US6358827 Method of forming a squared-off, vertically oriented polysilicon spacer gate
03/19/2002US6358826 Device improvement by lowering LDD resistance with new spacer/silicide process
03/19/2002US6358825 Process for controlling lifetime in a P-I-N diode and for forming diode with improved lifetime control
03/19/2002US6358824 Integrated circuits with tub-ties and shallow trench isolation
03/19/2002US6358823 Method of fabricating ion implanted doping layers in semiconductor materials and integrated circuits made therefrom
03/19/2002US6358822 Method of epitaxially growing III-V compound semiconductor containing nitrogen and at least another group V element utilizing MBE
03/19/2002US6358821 Sputtering metal on backside of wafer to form layer using aluminum or with copper and/or silicon
03/19/2002US6358820 Method of manufacturing semiconductor device
03/19/2002US6358819 Vapor deposition barrier oxides, masking, photoresists, ion implanting removal and heating
03/19/2002US6358818 Method for forming trench isolation regions
03/19/2002US6358817 Semiconductor storage unit and method of manufacturing the same
03/19/2002US6358816 Method for uniform polish in microelectronic device
03/19/2002US6358815 Semiconductor device and method of manufacturing the same
03/19/2002US6358814 Method for manufacturing semiconductor devices having an epitaxial layer and wafer alignment marks
03/19/2002US6358813 Method for increasing the capacitance of a semiconductor capacitors
03/19/2002US6358812 Methods of forming storage capacitors
03/19/2002US6358811 Method for forming a stoichiometric ferroelectric and/or dielectric thin film layer containing lead or bismuth on an electrode
03/19/2002US6358810 Method for superior step coverage and interface control for high K dielectric capacitors and related electrodes
03/19/2002US6358809 Method of modifying properties of deposited thin film material
03/19/2002US6358808 Semiconductor element with thermally nitrided film on high resistance film and method of manufacturing the same
03/19/2002US6358807 Bipolar semiconductor device and method of forming same having reduced transient enhanced diffusion
03/19/2002US6358806 Silicon carbide CMOS channel
03/19/2002US6358805 Method of making a SOI device having fixed channel threshold voltage
03/19/2002US6358804 Forming thin films by applying a solution of dielectric, heat-curing resin, evaporating the solvent and curing; where the solution contains gas generating additives or solvents that cause dedensification and lower dielectric constant
03/19/2002US6358803 Method of fabricating a deep source/drain
03/19/2002US6358802 Method for manufacturing semiconductor device having a gate electrode film containing nitrogen
03/19/2002US6358801 Method and apparatus for trench isolation process with pad gate and trench edge spacer elimination
03/19/2002US6358800 Method of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limit
03/19/2002US6358799 Nonvolatile semiconductor memory device and method for fabricating the same, and semiconductor integrated circuit device
03/19/2002US6358798 Method for forming gate electrode by damascene process
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