Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2002
03/26/2002US6362877 Visual inspection supporting apparatus and printed circuit board inspecting apparatus, and methods of soldering inspection and correction using the apparatuses
03/26/2002US6362871 Lithographic apparatus
03/26/2002US6362865 Liquid crystal display apparatus and method for manufacturing liquid crystal display apparatus
03/26/2002US6362864 Vertical alignment liquid crystal display device having planarized substrate surface
03/26/2002US6362798 Transistor circuit, display panel and electronic apparatus
03/26/2002US6362665 Backwards drivable MOS output driver
03/26/2002US6362650 Method and apparatus for incorporating a multiplier into an FPGA
03/26/2002US6362641 Integrated circuit device and semiconductor wafer having test circuit therein
03/26/2002US6362636 Probe station having multiple enclosures
03/26/2002US6362635 Split resistor probe and method
03/26/2002US6362532 Semiconductor device having ball-bonded pads
03/26/2002US6362528 Semiconductor device and method of manufacturing the same
03/26/2002US6362527 Borderless vias on bottom metal
03/26/2002US6362526 Alloy barrier layers for semiconductors
03/26/2002US6362524 Edge seal ring for copper damascene process and method for fabrication thereof
03/26/2002US6362523 Semiconductor device
03/26/2002US6362518 Electronic compoment to be mounted on a circuit board having electronic circuit device sealed therein and method of manufacturing the same
03/26/2002US6362514 Semiconductor device
03/26/2002US6362511 MIS-type semiconductor device having a multi-portion gate electrode
03/26/2002US6362510 Semiconductor topography having improved active device isolation and reduced dopant migration
03/26/2002US6362509 Field effect transistor with organic semiconductor layer
03/26/2002US6362508 Triple layer pre-metal dielectric structure for CMOS memory devices
03/26/2002US6362507 Electro-optical devices in which pixel section and the driver circuit are disposed over the same substrate
03/26/2002US6362506 Minimization-feasible word line structure for DRAM cell
03/26/2002US6362504 Contoured nonvolatile memory cell
03/26/2002US6362503 Low temperature process for fabricating layered superlattice materials and making electronic devices including same
03/26/2002US6362502 DRAM cell circuit
03/26/2002US6362501 DRAM cell array not requiring a device isolation layer between cells
03/26/2002US6362500 Memory structure in ferroelectric nonvolatile memory and readout method therefor
03/26/2002US6362499 Ferroelectric transistors using thin film semiconductor gate electrodes
03/26/2002US6362497 Semiconductor integrated circuit having ESD/EOS protection
03/26/2002US6362496 Semiconductor light emitting device having a GaN-based semiconductor layer, method for producing the same and method for forming a GaN-based semiconductor layer
03/26/2002US6362494 Semiconductor device and method and apparatus for manufacturing semiconductor device
03/26/2002US6362490 Ion implanter
03/26/2002US6362487 Method and device for nondestructive detection of crystal defects
03/26/2002US6362474 Semiconductor sample for transmission electron microscope and method of manufacturing the same
03/26/2002US6362437 Mounting structure of integrated circuit device having high effect of buffering stress and high reliability of connection by solder, and method of mounting the same
03/26/2002US6362436 Printed wiring board for semiconductor plastic package
03/26/2002US6362435 Multi-layer conductor pad for reducing solder voiding
03/26/2002US6362117 Method of making integrated circuit with closely spaced components
03/26/2002US6362116 Method for controlling photoresist baking processes
03/26/2002US6362114 Semiconductor processing methods of forming an oxynitride film on a silicon substrate
03/26/2002US6362113 Method of forming pattern
03/26/2002US6362112 Single step etched moat
03/26/2002US6362111 Tunable gate linewidth reduction process
03/26/2002US6362110 Enhanced resist strip in a dielectric etcher using downstream plasma
03/26/2002US6362109 Oxide/nitride etching having high selectivity to photoresist
03/26/2002US6362108 Composition for mechanical chemical polishing of layers in an insulating material based on a polymer with a low dielectric constant
03/26/2002US6362106 Chemical mechanical polishing method useful for copper substrates
03/26/2002US6362105 Method and apparatus for endpointing planarization of a microelectronic substrate
03/26/2002US6362104 Chemical mechanical polishing of a metal e.g titanium, aluminum, by using an oxidizer, photoactive solid catalyst, comprising a mixture of titanium dioxide and titanium trioxide, water and a pad.
03/26/2002US6362101 Chemical mechanical polishing methods using low pH slurry mixtures
03/26/2002US6362100 Methods and apparatus for forming a copper interconnect
03/26/2002US6362099 Providing a barrier layer having a first surface that is substantially unoxidized; depositing a first copper layer onto the first surface of the barrier layer, wherein the first copper layer is deposited from a precursor
03/26/2002US6362098 Plasma-enhanced chemical vapor deposition (CVD) method to fill a trench in a semiconductor substrate
03/26/2002US6362097 Collimated sputtering of semiconductor and other films
03/26/2002US6362095 Nickel silicide stripping after nickel silicide formation
03/26/2002US6362094 Hydrogenated silicon carbide as a liner for self-aligning contact vias
03/26/2002US6362093 Dual damascene method employing sacrificial via fill layer
03/26/2002US6362092 Planarization method on a damascene structure
03/26/2002US6362091 Method for making a semiconductor device having a low-k dielectric layer
03/26/2002US6362090 Plating copper on a copper pad via electroless plating to form a copper plated layer; plating nickel on said copper plated layer via electroless plating to form a nickel plated layer
03/26/2002US6362089 Providing semiconductor substrate; cleaning bonding surface of copper; activating bonding surface a first time in palladium bath; activating bonding surface a second time in electroless nickel-boron bath; depositing solderable/wirebondable metal
03/26/2002US6362088 Method of forming ohmic conductive components in a single chamber process
03/26/2002US6362087 Forming barrier layer on substrate; forming barrier layer on redistribution pattern and forming terminal electrode layer
03/26/2002US6362086 Forming a conductive structure in a semiconductor device
03/26/2002US6362085 Method for reducing gate oxide effective thickness and leakage current
03/26/2002US6362082 Methodology for control of short channel effects in MOS transistors
03/26/2002US6362081 Method to improve resistance uniformity and repeatability for low energy ion implantation
03/26/2002US6362080 Formation of a vertical junction through process simulation based optimization of implant doses and energies
03/26/2002US6362079 Semiconductor device and method of anodization for the semiconductor device
03/26/2002US6362078 Dynamic threshold voltage device and methods for fabricating dynamic threshold voltage devices
03/26/2002US6362077 Structure comprising a thin layer of material made up of conductive zones and insulating zones and a method of manufacturing such a structure
03/26/2002US6362076 Method of fabricating an SOI wafer by hydrogen ion delamination without independent bonding heat treatment
03/26/2002US6362075 Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide
03/26/2002US6362074 Integrated circuit processing with improved gate electrode fabrication
03/26/2002US6362073 Method for forming semiconductor device having low parasite capacitance using air gap and self-aligned contact plug
03/26/2002US6362072 Process for realizing trench structures
03/26/2002US6362071 Method for forming a semiconductor device with an opening in a dielectric layer
03/26/2002US6362070 Process for manufacturing a SOI wafer with buried oxide regions without cusps
03/26/2002US6362069 Long-wavelength VCSELs and method of manufacturing same
03/26/2002US6362068 Electrode interface for high-dielectric-constant materials
03/26/2002US6362066 Method for manufacturing bipolar devices
03/26/2002US6362065 Blocking of boron diffusion through the emitter-emitter poly interface in PNP HBTs through use of a SiC layer at the top of the emitter epi layer
03/26/2002US6362064 Elimination of walkout in high voltage trench isolated devices
03/26/2002US6362063 Formation of low thermal budget shallow abrupt junctions for semiconductor devices
03/26/2002US6362062 Disposable sidewall spacer process for integrated circuits
03/26/2002US6362061 Method to differentiate source/drain doping by using oxide slivers
03/26/2002US6362060 Method for forming semiconductor device having a gate in the trench
03/26/2002US6362059 Production of a semiconductor device having a P-well
03/26/2002US6362058 Method for controlling an implant profile in the channel of a transistor
03/26/2002US6362057 Method for forming a semiconductor device
03/26/2002US6362056 Method of making alternative to dual gate oxide for MOSFETs
03/26/2002US6362055 Method of gate doping by ion implantation
03/26/2002US6362054 Method for fabricating MOS device with halo implanted region
03/26/2002US6362053 Flow process for producing non-volatile memories with differentiated removal of the sacrificial oxide
03/26/2002US6362052 Use of an etch to reduce the thickness and around the edges of a resist mask during the creation of a memory cell
03/26/2002US6362051 Reliability
03/26/2002US6362050 Method for forming a non-volatile memory cell that eliminates substrate trenching
03/26/2002US6362049 High yield performance semiconductor process flow for NAND flash memory products
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