Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
04/2002
04/18/2002US20020043712 Circuit structure integrating the power distribution functions of circuits and leadframes into the chip surface
04/18/2002US20020043711 Stereolithographic method and apparatus for fabricating stabilizers for flip-chip type semiconductor devices and resulting structures
04/18/2002US20020043707 Semiconductor device incorporating hemispherical solid immersion lens, apparatus and method for manufacturing the same
04/18/2002US20020043704 Tape for chip on film and semiconductor therewith
04/18/2002US20020043703 Injection mold for an optical semiconductor package and corresponding optical semiconductor package
04/18/2002US20020043700 Semiconductor device and method for manufacturing the same
04/18/2002US20020043699 Semiconductor device
04/18/2002US20020043697 Schottky barrier field effect transistor large in withstanding voltage and small in distortion and return-loss
04/18/2002US20020043695 Method for forming an ultra thin dielectric film and a semiconductor device incorporating the same
04/18/2002US20020043694 Semiconductor raised source-drain structure
04/18/2002US20020043693 Dense backplane cell for configurable logic
04/18/2002US20020043692 Semiconductor storage device
04/18/2002US20020043691 Method for fabrication of field effect transistor
04/18/2002US20020043690 Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition
04/18/2002US20020043689 Surface-channel metal-oxide semiconductor transistors, their complementary field-effect transistors and method of producing the same
04/18/2002US20020043688 Integrated circuit provided with overvoltage protection and method for manufacture thereof
04/18/2002US20020043687 Semiconductor input protection circuit
04/18/2002US20020043686 Silicon-on-insulator chip having an isolation barrier for reliability
04/18/2002US20020043683 Semiconductor device and its manufacturing method
04/18/2002US20020043682 Non-volatile memory and semiconductor device
04/18/2002US20020043681 Hole-type storage cell structure and method for making the structure
04/18/2002US20020043680 Semiconductor integrated circuit device and process for manufacturing the same
04/18/2002US20020043679 Production of semiconductor integrated circuit
04/18/2002US20020043677 Ferroelectric capacitor and method for fabricating the same
04/18/2002US20020043676 Semiconductor device and method for driving the same
04/18/2002US20020043675 Memory device incorporating therein a HfO2 layer as a barrier layer
04/18/2002US20020043673 Semiconductor device and method for fabricating the same
04/18/2002US20020043672 Semiconductor device with a thin-film sensing area and device fabrication method
04/18/2002US20020043670 Integrated circuit with circuit elements having different supply voltages
04/18/2002US20020043669 Semiconductor device
04/18/2002US20020043667 Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device
04/18/2002US20020043666 Oxidizing silicon substrate; depositing metal or alloy; annealing to form silicate
04/18/2002US20020043665 Semiconductor device and a method of manufacturing the same
04/18/2002US20020043664 Semiconductor device
04/18/2002US20020043662 Semiconductor device
04/18/2002US20020043660 Semiconductor device and fabrication method therefor
04/18/2002US20020043658 Apparatus and methods of packaging and testing die
04/18/2002US20020043644 Selective silicon oxide etchant formulation including fluoride salt, chelating agent, and glycol solvent
04/18/2002US20020043630 Aluminum implantation method
04/18/2002US20020043629 Process for electron beam lithography, and electron-optical lithography system
04/18/2002US20020043615 Optical proximity effect correcting method and mask data forming method in semiconductor manufacturing process, which can sufficiently correct optical proximity effect, even under various situations with regard to size and shape of design pattern, and space width and position relation between design patterns
04/18/2002US20020043561 Method of and system for producing digital images of objects with subtantially reduced speckle-noise patterns by illuminating said objects with spatially and/or temporally coherent-reduced planar laser illumination
04/18/2002US20020043550 Wire bonding apparatus and discharge method thereof
04/18/2002US20020043548 Non-conductive and self-leveling leadframe clamp insert for wirebonding integrated circuits
04/18/2002US20020043541 Photoresist developing nozzle, photoresist developing apparatus, and photoresist developing method
04/18/2002US20020043539 Disposable syringe dispenser system
04/18/2002US20020043528 Ceramic heater
04/18/2002US20020043527 Ceramic heater
04/18/2002US20020043526 System and method for efficiently implementing a thermal processing chamber
04/18/2002US20020043488 Method and apparatus for the distribution of treatment liquids
04/18/2002US20020043468 Source of metal ions, an electrolyte and one or more branched suppressor compounds comprising branched polymers, dendrimers or star polymers
04/18/2002US20020043466 Depositing conductive barrier layer on substrate, depositing a conductive material on the substrate, and then depositing a second conductive material on the first by electroless deposition to fill discontinuities formed in seed layer
04/18/2002US20020043457 Sputtering apparatus
04/18/2002US20020043401 Semiconductor packages and methods for making the same
04/18/2002US20020043396 Connection method and connection structure of pad electrodes, and inspecting methods for connection state thereof
04/18/2002US20020043389 Virtual gate design for thin packages
04/18/2002US20020043364 Heat radiator for electronic device and method of making it
04/18/2002US20020043359 Heat sink for electronic parts and manufacture thereof
04/18/2002US20020043343 System and method for making aerated concrete sheets and using magnetic field to flatten a saw blade
04/18/2002US20020043341 Plasma process apparatus
04/18/2002US20020043340 Apparatus for processing samples
04/18/2002US20020043339 Apparatus for processing samples
04/18/2002US20020043338 Plasma etching apparatus and plasma etching method
04/18/2002US20020043337 Low mass wafer support system
04/18/2002US20020043335 Dry etching device
04/18/2002US20020043331 Method for manufacturing a group III nitride compound semiconductor device
04/18/2002US20020043274 Processing a semiconductor wafer in a chamber having upper and lower chambers, decoupling upper from lower chamber, cleaning upper chamber, determining that a leak rate and particle count for upper chamber meets predetermined criteria
04/18/2002US20020043272 Immersing a wafer in water, the wafer has front and back faces, and an edge, includes a particle free environment adjacent to front face and back face as liquid is being removed
04/18/2002US20020043216 Atomic layer deposition method and semiconductor device fabricating apparatus having rotatable gas injectors
04/18/2002US20020043215 Liquid substance supply device for vaporizing system, vaporizer, and vaporization performance appraisal method
04/18/2002US20020043214 Treatment solution supply apparatus and treatment solution supply method
04/18/2002US20020043209 Method of fabricating compound semiconductor device
04/18/2002US20020043208 Crystal growth method
04/18/2002US20020043163 Low distortion kinematic reticle support
04/18/2002US20020043027 Preventing formation of pits in copper wiring in chemical mechanical polishing of substrates for semiconductors, photomasks and memory hard disks
04/18/2002US20020043026 Chemical mechanical polishing; composition includes oxidizing agent, an inhibitor of a polyalkyleneimine, and a pH buffer
04/18/2002DE3828700C2 Kupferplattierter Leiterrahmen für Halbleiter-Kunststoff-Gehäuse Copper-lead frame for semiconductor plastic housing
04/18/2002DE10146936A1 Herstellverfahren für eine Chipkomponenten-Baugruppe Manufacturing method of a chip component assembly
04/18/2002DE10144700A1 Non-volatile semiconductor memory arrangement e.g. MONOS- and NMOS-types, has memory zone regions overlapping ends of channel forming zone
04/18/2002DE10143175A1 Spannfutter zum Halten einer zu testenden Vorrichtung A chuck for supporting a device under test
04/18/2002DE10143174A1 Meßstation Measuring station
04/18/2002DE10133646A1 Magnetic thin film memory has word line current control circuit, which forms and breaks current path of write word line corresponding to writing and reading data
04/18/2002DE10130999A1 Multifunktions-Reinigungsmodul einer Herstellungseinrichtung für Flachbildschirme und Reinigungsgerät mit Verwendung desselben The same multi-function cleaning module a manufacturing facility for flat screens and cleaner with use
04/18/2002DE10125004A1 Halbleiter-Bauelement Semiconductor component
04/18/2002DE10122976A1 Verfahren zum Ausbilden eines selbstjustierenden Kontakts und Herstellungsverfahren für eine Halbleitervorrichtung mit einem selbstjustierenden Kontakt A method for forming a self-aligned contact and manufacturing method of a semiconductor device with a self-aligned contact
04/18/2002DE10101948A1 Verfahren zum Anordnen eines Halbleiterchips auf einem Substrat und auf einem Substrat montierbarer Halbleiterbaustein A method for disposing a semiconductor chip on a substrate and on a substrate mountable semiconductor module
04/18/2002DE10051338A1 Liquid-cooling device for high-power semiconductor module, has housing with cooling surface and enclosing a liquid-flowed space
04/18/2002DE10051049A1 Semiconductor substrate made from silicon carbide has a p-doped layer, a silicon dioxide layer grown by depositing from the gas phase onto a p-doped silicon carbide layer, and several contact structures applied using photolithography
04/18/2002DE10050799A1 Semiconductor substrate made from silicon carbide has an n-doped layer, a silicon dioxide layer grown by depositing from the gas phase onto an n-doped silicon carbide layer, and several contact structures applied using photolithography
04/18/2002DE10049861A1 Semiconductor element has doped areas embedded in surface of semiconductor body forming pattern, which is not adjusted to pattern of semiconductor base body
04/18/2002DE10048809A1 Determining maximum positional error of structural elements on wafer
04/18/2002DE10048782A1 Determining maximum positional errors of structures on wafers employs virtual wafer and wafer parameter model to differentiate between rejection and rework
04/18/2002DE10048437A1 Verfahren zum Herstellen eines Körpers aus Halbleitermaterial mit reduzierter mittlerer freier Weglänge und mit dem Verfahren hergestellter Körper A method of manufacturing a body of semiconductor material with reduced mean free path length and produced by the method body
04/18/2002DE10048420A1 Verfahren zum Herstellen von integrierten Schaltungsanordnungen sowie zugehörige Schaltungsanordnungen, insbesondere Tunnelkontaktelemente A method for producing integrated circuit devices and associated circuitry, in particular tunnel contact elements
04/18/2002DE10047171A1 Electrode and/or conductor track used for components of OFETs and OLEDs is produced by treating an organic functional polymer with a chemical compound
04/18/2002DE10047133A1 Doped semiconductor material body e.g. for power semiconductors, has extended minority carrier life-time in relatively lower pressure region compared to that in relatively higher pressure region
04/18/2002DE10046933A1 Process for the chemical-mechanical polishing of silicon wafers comprises rotating a silicon surface to be cleaned on a polishing plate covered with a polishing cloth with continuous
04/18/2002DE10046899A1 Chip-Zuführeinrichtung und Verfahren zum Zuführen von Halbleiterchips Chip supply means and method for feeding semiconductor chips
04/18/2002DE10046782A1 Layer system used, e.g., in a moment filter or magnetic sensor comprises a ferromagnetic layer made of group 3D transition metals, and a fixing layer made of group 4D or 5D transition metals
04/18/2002DE10046302A1 Production of an active region over a deep trench capacitor comprises forming a capacitor in a semiconductor substrate, structuring and etching to form the active region, and wet etching the capacitor and the active region