Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
04/2002
04/25/2002US20020048971 Manufacturing method of semiconductor integrated circuit device
04/25/2002US20020048970 Method of controlling a shape of an oxide layer formed on a substrate
04/25/2002US20020048969 Method of forming film, method of manufacturing semiconductor device, and film forming apparatus
04/25/2002US20020048968 Porous silicon oxycarbide integrated circuit insulator
04/25/2002US20020048967 Fabrication process of a semiconductor integrated circuit device
04/25/2002US20020048965 Method of oxidzing a silicon surface
04/25/2002US20020048964 Growth promoting film is partially formed on a substrate having a portion which acts as a growth suppressing film on a surface thereof, and a nitride compound semiconductor film of a single crystal is grown thereon.
04/25/2002US20020048963 Plasma enhanced chemical vapor deposition process
04/25/2002US20020048962 Method for manufacturing a functional device by forming 45-degree-surface on (100) silicon
04/25/2002US20020048961 Semiconductor device and method for manufacturing semiconductor device
04/25/2002US20020048960 Endpoint detection in the etching of dielectric layers
04/25/2002US20020048959 Diamond as a polish-stop layer for chemical-mechanical planarization in a damascene process flow
04/25/2002US20020048958 Cleaning exposed surfaces of said conductive film and said barrier film; washing using a rinsing liquid; polishing until a portion of said insulator film is exposed; and washing exposed surfaces
04/25/2002US20020048957 Method of cleaning a polishing pad conditioner and apparatus for performing the same
04/25/2002US20020048956 Method and apparatus for shaping semiconductor surfaces
04/25/2002US20020048955 Method for fabricating a thin, free-standing semiconductor device layer and for making a three-dimensionally integrated circuit
04/25/2002US20020048954 Contact structure and production method thereof and probe contact assembly using same
04/25/2002US20020048953 Selectively etching unwanted metal deposits on a surface of a wafer; etching solution comprising citric acid and an oxidizing agent, espeically hydrogen peroxide.
04/25/2002US20020048952 Hard Mask for copper plasma etch
04/25/2002US20020048951 Method includes applying either a pre-flux or a cover sheet over the solder ball mounting pads that prevents the solder ball mounting pads being plated with gold.
04/25/2002US20020048950 Application of vapor phase HFACAC-based compound for use in copper decontamination and cleaning processes
04/25/2002US20020048949 Method of forming a metal wiring in a semiconductor device
04/25/2002US20020048948 Tape having implantable conductive lands for semiconductor packaging process and method for manufacturing the same
04/25/2002US20020048947 Semiconductor integrated circuit device and the process of the same
04/25/2002US20020048946 Local interconnect structures for integrated circuits and methods for making the same
04/25/2002US20020048945 Method for manufacturing semiconductor devices
04/25/2002US20020048944 Multi-level circuit structure
04/25/2002US20020048942 Method of manufacturing semiconductor device with two step formation of contact hole
04/25/2002US20020048941 Process for producing semiconductor integrated circuit device
04/25/2002US20020048940 Depositing a metal film at a first set of process conditions; and continuing to deposit the metal film at a second set of process conditions that are different from the first set of conditions.
04/25/2002US20020048939 A low step coverage plasma-enhanced oxide layer is formed between a polygate and a gate spacer; a gap, which is broad at the top and narrow at the bottom, is formed;metal silicide formed on exposed polygate surface
04/25/2002US20020048938 Crystal grains of large grain sizes can be formed by using a gas containing hydrogen and a borane, such as diborane, for forming a tungsten film
04/25/2002US20020048937 Method of forming a conductive contact
04/25/2002US20020048936 Metal layer in semiconductor device and method for fabricating the same
04/25/2002US20020048935 Semiconductor device and method for manufacturing the same
04/25/2002US20020048934 Planarization method on a damascene structure
04/25/2002US20020048933 Technique for intralevel capacitive isolation of interconnect paths
04/25/2002US20020048932 Semiconductor Processing Methods of Forming Integrated Circuity
04/25/2002US20020048931 Damascene structure and method of making
04/25/2002US20020048930 Interconnects are held to a minimum in length by using polyimide or polyarylenecyclobutane as an intermetal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment
04/25/2002US20020048929 Method of producing an interconnect structure for an integrated circuit
04/25/2002US20020048928 Semiconductor device and method for fabricating the same
04/25/2002US20020048926 Method for forming a self-aligned copper capping diffusion barrier
04/25/2002US20020048925 Attaching bond wires between a package and a semiconductor device that is sensitive to particles generated by the bond out process.
04/25/2002US20020048924 For connecting a nonconducting substrate and a chip without lateral shorting
04/25/2002US20020048921 A diffusion region is formed in semiconductive material, conductive line is formed which is laterally spaced from the diffusion region; integrated memory circuitry
04/25/2002US20020048920 Semiconductor processing methods of forming a conductive gate and line
04/25/2002US20020048919 Inactivating ions are implanted only to the source region of the semiconductor layer, to damage the crystal near the surface of the semiconductor layer, promoting siliciding reaction; parasitic resistance reduced
04/25/2002US20020048918 Forming two layers, etching the top one and oxidizing to form a notch, where the bottom layer oxidizes at a faster rate than the top layer; making a transistor gate
04/25/2002US20020048917 Semiconductor device and method of fabricating same
04/25/2002US20020048916 Thinned, stackable semiconductor device having low profile
04/25/2002US20020048914 Complementary metal oxide semiconductor (CMOS); transistor of a second conductivity type is Lateral MOS (LMOS) structure, and transistor of a first conductivity type is a Lateral Double-diffused (LDMOS) structure
04/25/2002US20020048913 Beam of ions directed at a glancing angle to a layer of dielectric (silicon oxide, SiO2) over a semiconductor so ions which are implanted into the semiconductor structure surface are scattered from the beam by the layer of SiO2
04/25/2002US20020048912 Low concentration drain region has two or more kinds of different impurity concentrations, and not by changing impurity distribution uniformly over whole low concentration drain regions, drain withstanding voltage improved
04/25/2002US20020048911 Selectively depositing polysilicon via chemical vapor deposition on the crystalline region and not the amorphous region of a substrate; conditions include chlorine gas-free and plasma-free
04/25/2002US20020048910 Method and apparatus for forming a semiconductor device utilizing a low temperature process
04/25/2002US20020048909 Process of vapor phase growth of nitride semiconductor
04/25/2002US20020048908 Of a semiconductor substrate, by drawing impurities to a localized region, measuring such as with mass spectrometry, and calculating bulk impurities based on localized levels
04/25/2002US20020048907 Methods of processing semiconductor wafer and producing IC card, and carrier
04/25/2002US20020048906 Semiconductor device, method of manufacturing the device and mehtod of mounting the device
04/25/2002US20020048905 Conductive resin film configured as a plurality of interconnect lines connected to the bump front electrodes; large number can be made at same time
04/25/2002US20020048904 Method of fabricating semiconductor device
04/25/2002US20020048903 Semiconductor device
04/25/2002US20020048902 Method for forming overlay verniers for semiconductor devices
04/25/2002US20020048901 Wafer thickness control during backside grind
04/25/2002US20020048900 Adding a reactive layer to a first material, adding a hydrophilic layer to a second material, joining and pressing; hydrophilic silicon to aluminum gallium arsenide layer for example
04/25/2002US20020048899 Process for forming shallow isolating regions in an integrated circuit and an integrated circuit thus formed
04/25/2002US20020048898 Method of forming active and isolation areas with split active patterning
04/25/2002US20020048897 Method of forming a self-aligned shallow trench isolation
04/25/2002US20020048896 Method of fabricating isolation trenches in a semiconductor substrate
04/25/2002US20020048895 Method of improving planarity of a photoresist
04/25/2002US20020048894 Transistor and process for fabricating the same
04/25/2002US20020048893 Semiconductor device having a metal gate with a work function compatible with a semiconductor device
04/25/2002US20020048892 Bipolar transistor with trenched-groove isolation regions
04/25/2002US20020048891 Method for crystallizing semiconductor material without exposing it to air
04/25/2002US20020048890 Sidewall spacer based fet alignment technology
04/25/2002US20020048889 Method of manufacturing semiconductor device with sidewall metal layers
04/25/2002US20020048888 Bombarding oxygen of silicon oxide and oxygen atoms proximate to said silicon oxide with an inert ion in an oxidizing atmosphere to increase thickness of silicon oxide
04/25/2002US20020048887 Method for fabricating semiconductor device
04/25/2002US20020048886 Semiconductor device and method for fabricating the same
04/25/2002US20020048885 Method for fabricating semiconductor device
04/25/2002US20020048884 Angled dopant implantation is followed by the formation of vertical trenches
04/25/2002US20020048883 Method of forming a semiconductor-on-insulator transistor
04/25/2002US20020048882 Capacitance coupling between the source and the floating gate forms a channel in the substrate, which is injected with hot electrons
04/25/2002US20020048881 Charge trapping within a floating gate transistor to indicate a 0 or 1 bit state
04/25/2002US20020048880 Method of manufacturing a semiconductor device including metal contact and capacitor
04/25/2002US20020048879 Structure of a lower electrode of a capacitor and a process for fabricating the same
04/25/2002US20020048878 Method of manufacturing capacitor in semiconductor devices
04/25/2002US20020048877 Forming a tantalum oxynitride film with a high dielectric constant on a rubidium film, and further forming an upper electrode
04/25/2002US20020048876 Method for fabricating capacitor of semiconductor device
04/25/2002US20020048875 Thin film transistors and methods of forming thin film transistors
04/25/2002US20020048874 Method for manufacturing semiconductor integrated circuit and semiconductor integrated circuit manufactured by this method
04/25/2002US20020048873 Semiconductor device and production thereof
04/25/2002US20020048871 Semiconductor device and manufacturing method therefor
04/25/2002US20020048870 Method of patterning noble metals for semiconductor devices by electropolishing
04/25/2002US20020048869 Method of forming semiconductor thin film and plastic substrate
04/25/2002US20020048868 Insulated gate field effect transistor and method for forming the same
04/25/2002US20020048867 Process for forming thin film transistor
04/25/2002US20020048865 Method of forming a local interconnect
04/25/2002US20020048864 Front and back sides of a film are irradiated with laser light from a solid state laser