| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 04/23/2002 | US6376384 Multiple etch contact etching method incorporating post contact etch etching |
| 04/23/2002 | US6376383 Method for etching silicon layer |
| 04/23/2002 | US6376382 Patterning a dielectric; etching |
| 04/23/2002 | US6376381 Planarizing solutions, planarizing machines, and methods for mechanical and/or chemical-mechanical planarization of microelectronic substrate assemblies |
| 04/23/2002 | US6376380 Method of forming memory circuitry and method of forming memory circuitry comprising a buried bit line array of memory cells |
| 04/23/2002 | US6376379 Method of hard mask patterning |
| 04/23/2002 | US6376378 Polishing apparatus and method for forming an integrated circuit |
| 04/23/2002 | US6376377 Post chemical mechanical polish (CMP) planarizing substrate cleaning method employing enhanced substrate hydrophilicity |
| 04/23/2002 | US6376376 Method to prevent CU dishing during damascene formation |
| 04/23/2002 | US6376375 Process for preventing the formation of a copper precipitate in a copper-containing metallization on a die |
| 04/23/2002 | US6376374 Process and manufacturing tool architecture for use in the manufacturing of one or more protected metallization structures on a workpiece |
| 04/23/2002 | US6376373 Method of manufacturing a semiconductor device |
| 04/23/2002 | US6376372 Approaches for mitigating the narrow poly-line effect in silicide formation |
| 04/23/2002 | US6376371 Method of forming a semiconductor device |
| 04/23/2002 | US6376370 Process for providing seed layers for using aluminum, copper, gold and silver metallurgy process for providing seed layers for using aluminum, copper, gold and silver metallurgy |
| 04/23/2002 | US6376369 Robust pressure aluminum fill process |
| 04/23/2002 | US6376368 Method of forming contact structure in a semiconductor device |
| 04/23/2002 | US6376367 Method for manufacturing multilayer interconnects by forming a trench with an underlying through-hole in a low dielectric constant insulator layer |
| 04/23/2002 | US6376366 Partial hard mask open process for hard mask dual damascene etch |
| 04/23/2002 | US6376365 Forming dielectric; etching a recess |
| 04/23/2002 | US6376364 Method of fabricating semiconductor device |
| 04/23/2002 | US6376363 Forming method of copper interconnection and semiconductor wafer with copper interconnection formed thereon |
| 04/23/2002 | US6376362 Production of semiconductor device |
| 04/23/2002 | US6376361 Method to remove excess metal in the formation of damascene and dual interconnects |
| 04/23/2002 | US6376360 Effective retardation of fluorine radical attack on metal lines via use of silicon rich oxide spacers |
| 04/23/2002 | US6376358 Method of forming plugs and local interconnect for embedded memory/system-on-chip (SOC) applications |
| 04/23/2002 | US6376357 Method for manufacturing a semiconductor device with voids in the insulation film between wirings |
| 04/23/2002 | US6376356 Method of manufacturing a metal wiring in a semiconductor device |
| 04/23/2002 | US6376355 Method for forming metal interconnection in semiconductor device |
| 04/23/2002 | US6376354 Wafer-level packaging process |
| 04/23/2002 | US6376353 Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects |
| 04/23/2002 | US6376352 Stud-cone bump for probe tips used in known good die carriers |
| 04/23/2002 | US6376351 High Fmax RF MOSFET with embedded stack gate |
| 04/23/2002 | US6376350 Method of forming low resistance gate electrode |
| 04/23/2002 | US6376349 Forming dielectric; then amorphous metal; siliciding |
| 04/23/2002 | US6376348 Reliable polycide gate stack with reduced sheet resistance and thickness |
| 04/23/2002 | US6376347 Method of making gate wiring layer over semiconductor substrate |
| 04/23/2002 | US6376346 High voltage device and method for making the same |
| 04/23/2002 | US6376345 Process for manufacturing semiconductor integrated circuit device |
| 04/23/2002 | US6376344 Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device |
| 04/23/2002 | US6376343 Reduction of metal silicide/silicon interface roughness by dopant implantation processing |
| 04/23/2002 | US6376342 Method of forming a metal silicide layer on a source/drain region of a MOSFET device |
| 04/23/2002 | US6376341 Optimization of thermal cycle for the formation of pocket implants |
| 04/23/2002 | US6376340 Methods for forming polycrystalline silicon film |
| 04/23/2002 | US6376339 Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on silicon carbide substrates by lateral growth from sidewalls of masked posts, and gallium nitride semiconductor structures fabricated thereby |
| 04/23/2002 | US6376338 Manufacturing method of a semiconductor device having a diffraction grating |
| 04/23/2002 | US6376337 Epitaxial SiOx barrier/insulation layer |
| 04/23/2002 | US6376336 Frontside SOI gettering with phosphorus doping |
| 04/23/2002 | US6376335 Semiconductor wafer manufacturing process |
| 04/23/2002 | US6376333 Method of manufacturing flexible display with transfer from auxiliary substrate |
| 04/23/2002 | US6376332 Composite member and separating method therefor, bonded substrate stack and separating method therefor, transfer method for transfer layer, and SOI substrate manufacturing method |
| 04/23/2002 | US6376331 Method for manufacturing a semiconductor device |
| 04/23/2002 | US6376330 Dielectric having an air gap formed between closely spaced interconnect lines |
| 04/23/2002 | US6376328 Method for producing capacitor elements, and capacitor element |
| 04/23/2002 | US6376327 Formation of a capacitor with low leakage current |
| 04/23/2002 | US6376326 Method of manufacturing DRAM capacitor |
| 04/23/2002 | US6376325 Method for fabricating a ferroelectric device |
| 04/23/2002 | US6376324 Collar process for reduced deep trench edge bias |
| 04/23/2002 | US6376323 Fabrication of gate of P-channel field effect transistor with added implantation before patterning of the gate |
| 04/23/2002 | US6376322 Base-emitter region of a submicronic bipolar transistor |
| 04/23/2002 | US6376321 Method of making a pn-junction in a semiconductor element |
| 04/23/2002 | US6376320 Method for forming field effect transistor with silicides of different thickness and of different materials for the source/drain and the gate |
| 04/23/2002 | US6376319 Forming transistor |
| 04/23/2002 | US6376318 Method of manufacturing a semiconductor device |
| 04/23/2002 | US6376316 Method for manufacturing semiconductor integrated circuit device having deposited layer for gate insulation |
| 04/23/2002 | US6376315 Method of forming a trench DMOS having reduced threshold voltage |
| 04/23/2002 | US6376314 Method of semiconductor device fabrication |
| 04/23/2002 | US6376313 Integrated circuit having at least two vertical MOS transistors and method for manufacturing same |
| 04/23/2002 | US6376312 Formation of non-volatile memory device comprised of an array of vertical field effect transistor structures |
| 04/23/2002 | US6376311 Vertical double diffused MOSFET and method for manufacturing same |
| 04/23/2002 | US6376310 Fabrication method of nonvolatile memory device |
| 04/23/2002 | US6376309 Method for reduced gate aspect ratio to improve gap-fill after spacer etch |
| 04/23/2002 | US6376308 Process for fabricating an EEPROM device having a pocket substrate region |
| 04/23/2002 | US6376307 Method for fabricating NOR type memory cells of nonvolatile memory device |
| 04/23/2002 | US6376306 Method for forming non volatile memory structures on a semiconductor substrate |
| 04/23/2002 | US6376305 Method of forming DRAM circuitry, DRAM circuitry, method of forming a field emission device, and field emission device |
| 04/23/2002 | US6376304 Semiconductor memory device and a method for fabricating the same |
| 04/23/2002 | US6376303 Method of manufacturing a capacitor having oxide layers with different impurities and method of fabricating a semiconductor device comprising the same |
| 04/23/2002 | US6376302 Method for forming a DRAM capacitor having a high dielectric constant dielectric and capacitor made thereby |
| 04/23/2002 | US6376301 Methods of forming a capacitor and methods of forming a monolithic integrated circuit |
| 04/23/2002 | US6376300 Process of manufacturing trench capacitor having a hill structure |
| 04/23/2002 | US6376299 Capacitor for semiconductor memory device and method of manufacturing the same |
| 04/23/2002 | US6376298 Layout method for scalable design of the aggressive RAM cells using a poly-cap mask |
| 04/23/2002 | US6376296 High-voltage device and method for manufacturing high-voltage device |
| 04/23/2002 | US6376295 Method for manufacturing a semiconductor memory device with a fine structure |
| 04/23/2002 | US6376294 Method to define poly dog-bone for word line strapping contact at stitch area in embedded DRAM process |
| 04/23/2002 | US6376293 Shallow drain extenders for CMOS transistors using replacement gate design |
| 04/23/2002 | US6376292 Self-aligning photolithography and method of fabricating semiconductor device using the same |
| 04/23/2002 | US6376291 Process for manufacturing buried channels and cavities in semiconductor material wafers |
| 04/23/2002 | US6376290 Method of forming a semiconductor thin film on a plastic substrate |
| 04/23/2002 | US6376289 Method of manufacturing a semiconductor device |
| 04/23/2002 | US6376288 Method of forming thin film transistors for use in a liquid crystal display |
| 04/23/2002 | US6376287 Method of making field effect |
| 04/23/2002 | US6376286 Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer |
| 04/23/2002 | US6376285 Annealed porous silicon with epitaxial layer for SOI |
| 04/23/2002 | US6376284 Method of fabricating a memory device |
| 04/23/2002 | US6376281 Multilayer; metal or alloy layer, bonding layer and backing plate |
| 04/23/2002 | US6376278 Methods for making a plurality of flip chip packages with a wafer scale resin sealing step |
| 04/23/2002 | US6376277 Semiconductor package |
| 04/23/2002 | US6376276 Method of preparing diamond semiconductor |