Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2002
05/21/2002US6392310 Semiconductor device having a reduced leakage current and a fabrication process thereof
05/21/2002US6392308 Semiconductor device having bumper portions integral with a heat sink
05/21/2002US6392307 Semiconductor device
05/21/2002US6392306 Semiconductor chip assembly with anisotropic conductive adhesive connections
05/21/2002US6392305 Chip scale package of semiconductor
05/21/2002US6392302 Polycide structure and method for forming polycide structure
05/21/2002US6392300 Semiconductor device having an alignment mark formed on the uppermost layer of a multilayer wire
05/21/2002US6392299 Integrated circuit and associated fabrication process
05/21/2002US6392295 Semiconductor device
05/21/2002US6392293 Semiconductor package with sloped outer leads
05/21/2002US6392292 Multi-level stacked semiconductor bear chips with the same electrode pad patterns
05/21/2002US6392291 Semiconductor component having selected terminal contacts with multiple electrical paths
05/21/2002US6392290 Vertical structure for semiconductor wafer-level chip scale packages
05/21/2002US6392289 Integrated circuit substrate having through hole markings to indicate defective/non-defective status of same
05/21/2002US6392287 Semiconductor package and fabricating method thereof
05/21/2002US6392286 Semiconductor chip packaging system and a semiconductor chip packaging method using the same
05/21/2002US6392285 Method for fabricating a capacitor device with BiCMOS process and the capacitor device formed thereby
05/21/2002US6392284 Capacitor/antifuse structure having a barrier-layer electrode and improved barrier layer
05/21/2002US6392283 Photodetecting device and method of manufacturing the same
05/21/2002US6392280 Metal gate with PVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process
05/21/2002US6392279 Semiconductor device having LDD structure adapted to lower parasitic capacitance and parasitic resistance
05/21/2002US6392278 Fet having a reliable gate electrode
05/21/2002US6392275 Semiconductor device with DMOS, BJT and CMOS structures
05/21/2002US6392274 High-voltage metal-oxide-semiconductor transistor
05/21/2002US6392272 Insulating gate type semiconductor device
05/21/2002US6392271 Structure and process flow for fabrication of dual gate floating body integrated MOS transistors
05/21/2002US6392270 Semiconductor device and method for manufacturing the device
05/21/2002US6392269 Non-volatile semiconductor memory and manufacturing method thereof
05/21/2002US6392268 Nonvolatile semiconductor storage apparatus and production method of the same
05/21/2002US6392267 Flash EPROM array with self-aligned source contacts and programmable sector erase architecture
05/21/2002US6392265 Ferroelectric film; low voltage
05/21/2002US6392264 Semiconductor memory device and method of producing the same
05/21/2002US6392262 Compound semiconductor device having low-resistive ohmic contact electrode and process for producing ohmic electrode
05/21/2002US6392261 Solid state imaging device and manufacturing method thereof
05/21/2002US6392259 Semiconductor chip with surface covering
05/21/2002US6392258 High speed heterojunction bipolar transistor, and RF power amplifier and mobile communication system using the same
05/21/2002US6392257 Mutlilayer; silicon, silicon oxide, strontium titanate and gallium asenide layers
05/21/2002US6392255 Display device having a thin film transistor and electronic device having such display device
05/21/2002US6392253 Semiconductor device with single crystal films grown on arrayed nucleation sites on amorphous and/or non-single crystal surfaces
05/21/2002US6392252 Semiconductor device
05/21/2002US6392245 Scanning wheel for ion implantation process chamber
05/21/2002US6392243 Electron beam exposure apparatus and device manufacturing method
05/21/2002US6392240 Sample table for pattern exposure machine
05/21/2002US6392230 Focused ion beam forming method
05/21/2002US6392205 Disc heater and temperature control apparatus
05/21/2002US6392202 Heating apparatus for bump bonding, bump bonding method and bump forming apparatus, and semiconductor wafer
05/21/2002US6392187 Apparatus and method for utilizing a plasma density gradient to produce a flow of particles
05/21/2002US6392163 Controlled-shaped solder reservoirs for increasing the volume of solder bumps
05/21/2002US6392158 Structure equipped with electric contacts formed through said structure substrate and method for obtaining said structure
05/21/2002US6392143 Flexible package having very thin semiconductor chip, module and multi chip module (MCM) assembled by the package, and method for manufacturing the same
05/21/2002US6391805 High-pressure anneal process for integrated circuits
05/21/2002US6391804 Method and apparatus for uniform direct radiant heating in a rapid thermal processing reactor
05/21/2002US6391803 Method of forming silicon containing thin films by atomic layer deposition utilizing trisdimethylaminosilane
05/21/2002US6391802 Method of manufacturing an integrated capacitor onto a silicon substrate
05/21/2002US6391801 Oxidizing tungsten nitride; forming field effect transistor
05/21/2002US6391800 Method for patterning a substrate with photoresist
05/21/2002US6391799 Process for fabricating a structure of semiconductor-on-insulator type in particular SiCOI
05/21/2002US6391798 Process for planarization a semiconductor substrate
05/21/2002US6391797 Method of manufacturing semiconductor device by sputtering dielectric forming materials while selectively heating growing layer
05/21/2002US6391796 Removing silicon dioxide film; high speed heating and cooling in hydrogen reducing atmosphere; semiconductors
05/21/2002US6391795 Low k dielectric composite layer for intergrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning
05/21/2002US6391794 Composition and method for cleaning residual debris from semiconductor surfaces
05/21/2002US6391793 Comprising ammonium fluoride, an inorganic acid component, and an oxidizing agent, at ph of seven to eight; use in forming isolation structures, shallow trench isolation
05/21/2002US6391792 Multi-step chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layer
05/21/2002US6391791 Dry-etching method and apparatus, photomasks and method for the preparation thereof, and semiconductor circuits and methods for the fabrication thereof
05/21/2002US6391790 Supplying radio frequency and biasing power; etching silicon based material with hydrogen-free fluorocarbon gas; semiconductors, integrated circuits
05/21/2002US6391789 Dry etching system for patterning target layer at high reproducibility and method of dry etching used therein
05/21/2002US6391788 Two etchant etch method
05/21/2002US6391787 Stepped upper electrode for plasma processing uniformity
05/21/2002US6391786 Etching process for organic anti-reflective coating
05/21/2002US6391785 Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
05/21/2002US6391784 Spacer-assisted ultranarrow shallow trench isolation formation
05/21/2002US6391783 Method to thin down copper barriers in deep submicron geometries by using alkaline earth element, barrier additives, or self assembly technique
05/21/2002US6391782 Process for forming multiple active lines and gate-all-around MOSFET
05/21/2002US6391781 Method of making a semiconductor device
05/21/2002US6391780 Method to prevent copper CMP dishing
05/21/2002US6391779 Planarization process
05/21/2002US6391778 Contact/via force fill techniques and resulting structures
05/21/2002US6391777 The second time, after the removal of excess copper by chemical mechanical polishing
05/21/2002US6391776 Method of depositing a copper seed layer which promotes improved feature surface coverage
05/21/2002US6391775 Method of forming embedded copper interconnections and embedded copper interconnection structure
05/21/2002US6391774 Fabrication process of semiconductor device
05/21/2002US6391773 Method and materials for through-mask electroplating and selective base removal
05/21/2002US6391772 Method for forming interconnects in semiconductor device
05/21/2002US6391771 Integrated circuit interconnect lines having sidewall layers
05/21/2002US6391770 Method of manufacturing semiconductor device
05/21/2002US6391769 Method for forming metal interconnection in semiconductor device and interconnection structure fabricated thereby
05/21/2002US6391768 Planarizing by chemical mechanical polishing after filling, oxidizing alkyl silane with hydrogen peroxide
05/21/2002US6391767 Dual silicide process to reduce gate resistance
05/21/2002US6391766 Method of making a slot via filled dual damascene structure with middle stop layer
05/21/2002US6391764 Method for fabricating semiconductor device
05/21/2002US6391763 Method for forming a plug or damascene trench on a semiconductor device
05/21/2002US6391762 Method of forming a microelectronic assembly with a particulate free underfill material and a microelectronic assembly incorporation the same
05/21/2002US6391761 Method to form dual damascene structures using a linear passivation
05/21/2002US6391760 Method of fabricating local interconnect
05/21/2002US6391759 Bonding method which prevents wire sweep and the wire structure thereof
05/21/2002US6391757 Dual damascene process
05/21/2002US6391756 Semiconductor processing methods of forming contact openings
05/21/2002US6391755 Method of making EEPROM transistor for a DRAM
05/21/2002US6391754 Method of making an integrated circuit interconnect
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