Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2002
05/30/2002WO2001074529A3 Laser system and method for single pass micromachining of multilayer workpieces
05/30/2002WO2001073957A3 Battery-operated wireless-communication apparatus and method
05/30/2002WO2001072629A3 Flexibly oriented ice dispenser
05/30/2002WO2001068939A3 Magnetically enhanced plasma etch process using a heavy fluorocarbon etching gas
05/30/2002WO2001063905A3 Frame shutter pixel with an isolated storage node
05/30/2002WO2001059804A3 Device and method for coupling two circuit components which have different impedances
05/30/2002WO2001046489A9 Ion beam modification of residual stress gradients in thin film polycrystalline silicon membranes
05/30/2002WO2001041201A9 Process for fabricating a uniform gate oxide of a vertical transistor
05/30/2002WO2001041181A9 Gas cluster ion beam smoother apparatus
05/30/2002WO2001035718A9 System and method for product yield prediction
05/30/2002WO2001032951A9 Chemical fluid deposition for the formation of metal and metal alloy films on patterned and unpatterned substrates
05/30/2002US20020066070 Semiconductor structures and manufacturing methods
05/30/2002US20020066002 Integrated magnetoresistive semiconductor memory and fabrication method for the memory
05/30/2002US20020065900 Method and apparatus for communicating images, data, or other information in a defect source identifier
05/30/2002US20020065643 Method for optimizing electromagnetic interference and method for analyzing the electromagnetic interference
05/30/2002US20020065616 Method for evaluating process chambers used for semiconductor manufacturing
05/30/2002US20020065572 Industrial machine management system and method
05/30/2002US20020065331 Having low dielectric constants useful in electronic component manufacture
05/30/2002US20020065242 Selective metallisation of nucleic acids via metal nanoparticles produced in-situ
05/30/2002US20020065204 Formulations including a 1,3-dicarbonyl compound chelating agent and copper corrosion inhibiting agents for stripping residues from semiconductor substrates containing copper structures
05/30/2002US20020065032 Polishing pad
05/30/2002US20020065025 Chemical mechanical polishing method for copper
05/30/2002US20020065023 Multilayered CMP stop for flat planarization
05/30/2002US20020065022 Polishing solution supply system, method of supplying polishing solution, apparatus for and method of polishing semiconductor substrate and method of manufacturing semiconductor device
05/30/2002US20020064970 Chemical vapor deposition; reacting a precursor such as metal alkoxide, metal alkoxide containing halogen, metal beta-diketonate, metal oxoacid, metal acetate, or metal alkene with oxidant gas, annealing for densification
05/30/2002US20020064969 Dielectric layer disposed inwardly from the contact layer and outwardly from the semiconductor device, the dielectric layer of porous doped dielectric material
05/30/2002US20020064968 Forming spacers on the sidewalls of the contact holes in the SOG layer decreases short circuiting between the pads when they are formed in the SOG insulating layer that contains impurities
05/30/2002US20020064967 Spin coating for maximum fill characteristic yielding a planarized thin film surface
05/30/2002US20020064965 Low dielectric constant polyorganosilicon coatings generated from polycarbosilanes
05/30/2002US20020064964 Method for forming damascene metal gate
05/30/2002US20020064963 For a surface such as semiconductors or liquid crystal displays to be treated by flowing the cleaner of a surfactant and an organic solvent at high speed; nondamaging
05/30/2002US20020064962 Method for improving electrical characteristics of oxide film grown on gallium arsenide by plasma treatment
05/30/2002US20020064961 Method and apparatus for dissolving a gas into a liquid for single wet wafer processing
05/30/2002US20020064959 ILD planarization method
05/30/2002US20020064958 Exposure method
05/30/2002US20020064956 Method of forming a storage node of a capacitor
05/30/2002US20020064955 Wafer polishing slurry and chemical mechanical polishing (CMP) method using the same
05/30/2002US20020064954 Configuration in which wafers are individually supplied to fabrication units and measuring units located in a fabrication cell
05/30/2002US20020064953 Organic polymer with dielectric constant of 4 or lower; for example polyarylene ethers
05/30/2002US20020064952 Staged aluminum deposition process for filling vias
05/30/2002US20020064951 Treatment of low-k dielectric films to enable patterning of deep submicron features
05/30/2002US20020064950 Method of making a semiconductor device
05/30/2002US20020064949 Produced by reactive sintering and vacuum hot pressing powders and products such as sputtering targets
05/30/2002US20020064948 Preparation method of bis (alkylcyclopentadienyl) ruthenium
05/30/2002US20020064946 Field effect transistor with silicide gate
05/30/2002US20020064945 Method for preparing semiconductor including formation of contact hole using difluoromethane gas
05/30/2002US20020064944 Method of manufacturing a contact of a semiconductor device using cluster apparatus having at least one plasma pretreatment module
05/30/2002US20020064943 Method of forming a trench isolation structure resistant to hot phosphoric acid by extending trench liner to shoulder portions
05/30/2002US20020064942 Low pressure, low temperature, semiconductor gap filling process
05/30/2002US20020064941 Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene
05/30/2002US20020064940 Forming opening in substrate, which may be a dielectric layer having a low k, forming passivation layer within opening and photoresist within the opening and over the passivation layer
05/30/2002US20020064939 Method for forming conductive line in semiconductor device
05/30/2002US20020064938 Method for fabricating semiconductor device
05/30/2002US20020064937 Methods of manufacturing integrated circuit devices in which a spin on glass insulation layer is dissolved so as to recess the spin on glass insulation layer from the upper surface of a pattern
05/30/2002US20020064936 Method of forming interlevel dielectric layer of semiconductor device
05/30/2002US20020064935 Insulating film covering semiconductor chip other than surfaces of conductive sections, film including stress buffering layer in lateral direction of conductive sections to relax stress applied to bumps
05/30/2002US20020064934 Method and structure for reducing contact aspect ratios
05/30/2002US20020064933 Method of forming solder bumps
05/30/2002US20020064931 Method and apparatus for applying a protective over-coating to a ball-grid-array (BGA) structure
05/30/2002US20020064930 Method for forming a solder bump, and process for fabricating a semiconductor device
05/30/2002US20020064929 Novel passivation structure and its method of fabrication
05/30/2002US20020064928 Method for manufacturing a high-frequency integrated circuit for reducing cross-talk and facilitating energy storage
05/30/2002US20020064927 Apparatus for forming strontium-tantalum-oxide thin film and a method thereof
05/30/2002US20020064926 Method for manufacturing encapsulated electronic components, particularly integrated circuits
05/30/2002US20020064925 CMOS device and method of manufacturing the same
05/30/2002US20020064924 Implanting ions into surface of substrate to desired depth, providing increasing global energy of substrate to initiate cleaving action
05/30/2002US20020064923 Semiconductor device and method for fabricating the same
05/30/2002US20020064922 High performance system-on-chip using post passivation process
05/30/2002US20020064921 Semiconductor integrated circuit device and a method of manufacturing the same
05/30/2002US20020064920 Methods of forming transistors and semiconductor processing methods of forming transistor gates
05/30/2002US20020064919 Forming spacer on sidewall of polysilicon gate, forming second spacer on sidewall of first spacer, performing anisotropic etching to remove portion of spacer, forming metal silicide
05/30/2002US20020064918 Doping integrated circuit components and a silicon substrate with nitrogen, depositing nickel, and annealing
05/30/2002US20020064917 Semiconductor integrated circuit device and method of manufacturing the same
05/30/2002US20020064916 Eeprom semiconductor device method and fabricating the same
05/30/2002US20020064915 Semiconductor device and method of forming the same
05/30/2002US20020064914 Method for patterning a metal or metal silicide layer and a capacitor structure fabricated by the method
05/30/2002US20020064913 Bulk, single crystalline where buried, doped glass is used as a mask to form deep trenches for storage in a bulk region
05/30/2002US20020064912 Semiconductor device having an improved isolation structure, and method of manufacturing the semiconductor device
05/30/2002US20020064911 Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
05/30/2002US20020064910 Split gate field effect transistor (FET) device with enhanced electrode registration and method for fabrication thereof
05/30/2002US20020064909 Self-assembled electrical networks
05/30/2002US20020064908 Semiconductor device and method of manufacturing the same
05/30/2002US20020064906 Three dimensional device integration method and integrated device
05/30/2002US20020064905 Wire bonding method and semiconductor package manufactured using the same
05/30/2002US20020064904 Connecting method of semiconductor element and semiconductor device
05/30/2002US20020064903 Semiconductor device, and a method of producing semiconductor device
05/30/2002US20020064902 Method for fabricating large area flexible electronics
05/30/2002US20020064901 Semiconductor device and manufacturing method thereof
05/30/2002US20020064900 Semiconductor device and method of fabricating the same
05/30/2002US20020064899 Semiconductor device substrate and semiconductor device fabrication method
05/30/2002US20020064898 Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device
05/30/2002US20020064894 Embedding and aligning a glass substrate and a transistor
05/30/2002US20020064893 Semiconductor device manufacturing method
05/30/2002US20020064892 Static charge dissipation pads for sensors
05/30/2002US20020064796 Generating preferential amino acid sequences on substrate; obtain substrate, deblock, expose to amino acids, recover preferential particles
05/30/2002US20020064731 Radiation-sensitive mixture and production of relief structures
05/30/2002US20020064729 Selective electroplating method employing annular edge ring cathode electrode contact
05/30/2002US20020064715 Increasing integration of semiconductor devices via narrowing the width of the pattern formed in the mask pattern and the distance between; photolithography; semiconductors; integrated circuits
05/30/2002US20020064714 Mask for manufacturing semiconductor device and method of manufacture thereof
05/30/2002US20020064675 Dual process semiconductor heterostructures