Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2002
05/16/2002WO2001075968A3 Method of manufacturing a heterojunction bicmos integrated circuit
05/16/2002WO2001071734A3 Multi-layer tunneling device with a graded stoichiometry insulating layer
05/16/2002WO2001055952A8 Method and system for collecting and transmitting chemical information
05/16/2002WO2001050161A9 CALCIUM FLUORIDE (CaF2) STRESS PLATE AND METHOD OF MAKING THE SAME
05/16/2002WO2001036901A9 Systems and methods for quantifying nonlinearities in interferometry systems
05/16/2002WO2001034765A9 Methods and apparatus for the electronic, homogeneous assembly and fabrication of devices
05/16/2002US20020059557 Method of forming fine patterns in semiconductor device
05/16/2002US20020059555 Depopulated programmable logic array
05/16/2002US20020059554 Design method for semiconductor integrated circuit device
05/16/2002US20020059547 Semiconductor integrated circuit including a test facilitation circuit for functional blocks intellectual properties and automatic insertion method of the same test facilitation circuit
05/16/2002US20020059513 System and method for configuring equipment
05/16/2002US20020059323 Synchronous dynamic random access memory
05/16/2002US20020059053 System verification equipment, system verification method and LSI manufacturing method using the system verification equipment
05/16/2002US20020059012 Method of manufacturing semiconductor devices
05/16/2002US20020059011 Implant monitoring using multiple implanting and annealing steps
05/16/2002US20020059010 Failure analyzing device for semiconductors
05/16/2002US20020058778 Used as an underfilling sealant between such a semiconductor device and a circuit board to which the semiconductor device is electrically connected
05/16/2002US20020058756 Underfill sealants with improved adhesion, improved resistance to moisture absorption and improved resistance to stress cracking
05/16/2002US20020058465 Method of abrading both faces of work piece
05/16/2002US20020058462 Chemical mechanical polishing of dielectric materials
05/16/2002US20020058461 Method and apparatus for polishing
05/16/2002US20020058460 Method of controlling wafer polishing time using sample-skip algorithm and wafer polishing using the same
05/16/2002US20020058426 Controlling a ratio of platen speed to carrier speed (PS to CS) within a specific range
05/16/2002US20020058425 Method of structuring a photoresist layer
05/16/2002US20020058424 Forming an amorphous region in the upper surface of a silicon substrate by exposing to halogen species; and forming a dielectric layer on said amorphous region.
05/16/2002US20020058423 Wet etching system for manufacturing semiconductor devices and wet etching method using the same
05/16/2002US20020058422 Stiction-free microstructure releasing method for fabricating MEMS device
05/16/2002US20020058421 Method for forming high quality multiple thickness oxide layers by reducing descum induced defects
05/16/2002US20020058419 Dry etching method and apparatus
05/16/2002US20020058418 Treatment of substrates
05/16/2002US20020058417 A) removing an oxide from a surface; and b) commencing application of a passivation layer to the surface within 5 seconds of the oxide removal.
05/16/2002US20020058416 Method for forming thin film and method for fabricating liquid crystal display using the same
05/16/2002US20020058415 Rough ruthenium layer or a rough ruthenium oxide layer used in conjunction with non-rough ruthenium and/or non-rough ruthenium oxide layers to form integrated circuits, for example, e.g., bottom electrode of a capacitor.
05/16/2002US20020058414 Methods for forming rough ruthenium-containing layers and structures/methods using same
05/16/2002US20020058413 Generation of RF plasma, temperature and pressure are controlled so as to form a primary film over the upper surface region of the insulating layer, over the insulating side wall regions, and over the exposed silicon region
05/16/2002US20020058412 Forming an Ni bump by non-electrolytic plating in an opening of an insulating protecting film formed on an electrode pad on a semiconductor substrate, and removing a plating solution residue
05/16/2002US20020058411 Semiconductor device having low dielectric layer and method of manufacturing thereof
05/16/2002US20020058410 Providing a mixing gas of nitrogen gas and hydrogen gas into the chamber and performing a rapid thermal anneal step for the gate unit, and performing a rapid thermal oxidation step for the gate unit.
05/16/2002US20020058409 Elimination of overhang in liner/barrier/seed layers using post-deposition sputter etch
05/16/2002US20020058408 Overlap of the line over the plug or via is minimized or eliminated.
05/16/2002US20020058407 Structure of critical dimension bar
05/16/2002US20020058406 Bump forming method and bump forming apparatus
05/16/2002US20020058405 A structure to reduce line-line capacitance with low k material
05/16/2002US20020058404 Methods of forming electrically conductive interconnections and electrically interconnected substrates
05/16/2002US20020058403 Method of forming overmolded chip scale package and resulting product
05/16/2002US20020058402 Method of forming an etch stop layer during manufacturing of a semiconductor device
05/16/2002US20020058401 Metal line deterioration due to electromigration is minimized to improve its reliability.
05/16/2002US20020058400 Method for manufacturing a semiconductor device, stencil mask and method for manufacturing the same
05/16/2002US20020058399 Semiconductor thin film and method of fabricating semiconductor thin film, apparatus for fabricating single crystal semiconductor thin film, and method of fabricating single crystal thin film, single crystal thin film substrate, and semiconductor device
05/16/2002US20020058398 Few-particle-induced low-pressure teos process
05/16/2002US20020058397 Hydrogen plasma photoresist strip and polymeric residue cleanup process for low dielectric constant materials
05/16/2002US20020058395 High density flip chip memory arrays
05/16/2002US20020058394 Semiconductor capacitors
05/16/2002US20020058393 Capacitor electrode having uneven surface formed by using hemispherical grained silicon
05/16/2002US20020058392 Forming silicon storage nodes on silicon substrates; heating the silicon substrate to a temperature sufficient to drive dopants from the doped oxide into the silicon layer
05/16/2002US20020058391 Capacitor for a semiconductor device and method for forming the same
05/16/2002US20020058390 Semiconductor device and method for fabricating the same
05/16/2002US20020058389 Reduced contact area of sidewall conductor
05/16/2002US20020058388 Bipolar junction device
05/16/2002US20020058387 SOI annealing method and SOI manufacturing method
05/16/2002US20020058386 Structure of a dram and a manufacturing process therefor
05/16/2002US20020058385 Semiconductor device and method for manufacturing the same
05/16/2002US20020058384 Laminated structure and a method of forming the same
05/16/2002US20020058383 Amorphous carbon layer for improved adhesion of photoresist and method of fabrication
05/16/2002US20020058382 Dual gate oxide process for deep submicron ICS
05/16/2002US20020058381 Method for manufacturing a nonvolatile memory
05/16/2002US20020058380 High storage capacitance
05/16/2002US20020058379 Semiconductor memory device and manufacturing method thereof
05/16/2002US20020058378 Method for manufacturing an mdl semiconductor device including a dram device having self-aligned contact hole and a logic device having dual gate structure
05/16/2002US20020058377 Exposing the tungsten nitride to N2 or ammonia plasma
05/16/2002US20020058376 Capacitor of a semiconductor device and method of manufacturing the same
05/16/2002US20020058375 Semiconductor device and method for fabricating the same
05/16/2002US20020058374 Method of forming dual-metal gates in semiconductor device
05/16/2002US20020058373 High gain bipolar junction transistor with counterdoped base in CMOS technology
05/16/2002US20020058372 Method for forming a gate in a semiconductor device
05/16/2002US20020058371 Method of manufacturing semiconductor device
05/16/2002US20020058370 Method for forming metal wire interconnection in semiconductor devices using dual damascene process
05/16/2002US20020058369 Semiconductor device and method for manufacturing the same
05/16/2002US20020058367 Substrate and the diffusion regions are not damaged during the etching amorphous silicon layer
05/16/2002US20020058366 Thin-film semiconductor device fabrication method
05/16/2002US20020058365 Active layer of a thin film transistor can be crystallized into single crystalline silicon by filtering a crystal component having a uniform crystal orientation from a poly-crystal region
05/16/2002US20020058364 Semiconductor device and manufacturing method thereof
05/16/2002US20020058363 Process for manufacturing semiconductor integrated circuit device
05/16/2002US20020058362 Active matrix type display device and method of manufacturing the same
05/16/2002US20020058361 Region for eliminating carriers in the vicinity of the channel region of the silicon on insulator transistor such as a lattice defects
05/16/2002US20020058360 Method of encapsulating semiconductor devices utilizing a dispensing apparatus with rotating orifices
05/16/2002US20020058358 Method and structure for manufacturing improved yield semiconductor packaged devices
05/16/2002US20020058357 Die attaching method
05/16/2002US20020058355 System for integrating a toroidal inductor in a semiconductor device
05/16/2002US20020058352 Monolithic lead-salt infrared radiation detectors and methods of formation
05/16/2002US20020058351 Method of manufacturing semiconductor device having ZnO based oxide semiconductor layer
05/16/2002US20020058349 Method of producing nitride-based heterostructure devices
05/16/2002US20020058348 Pattern formation method using two alternating phase shift masks
05/16/2002US20020058347 Semiconductor package with a controlled impedance bus and method of forming same
05/16/2002US20020058345 Apparatus and method for removing an organic material from a semiconductor device
05/16/2002US20020058343 Evaluation method of ferroelectric capacitor and wafer mounted with evaluation element
05/16/2002US20020058331 Method and apparatus for hybridization
05/16/2002US20020058204 Planarizing underlayers for multilayer lithography are characterized by the presence of a polymer containing a cyclic ether monomer, a saturated polycyclic monomer, and aromatic monomer, and an acid generator
05/16/2002US20020058203 Chemically amplified resist compositions
05/16/2002US20020058202 Positive-working photoresist composition and photosensitive material using same