| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 05/21/2002 | US6391753 Process for forming gate conductors |
| 05/21/2002 | US6391752 Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane |
| 05/21/2002 | US6391751 Method for forming vertical profile of polysilicon gate electrodes |
| 05/21/2002 | US6391750 Method of selectively controlling contact resistance by controlling impurity concentration and silicide thickness |
| 05/21/2002 | US6391749 Selective epitaxial growth method in semiconductor device |
| 05/21/2002 | US6391748 Surface free of amorphous silicon nitride; aluminum nitride layer grown by subjecting the silicon substrate to background ammonia followed by repetitively alternating the flux of 1) al without ammonia and 2) ammonia without al |
| 05/21/2002 | US6391747 Method for forming polycrystalline silicon film |
| 05/21/2002 | US6391746 Which collect electrons or holes, depending on polarity of current collector |
| 05/21/2002 | US6391745 Method for forming overlay verniers for semiconductor devices |
| 05/21/2002 | US6391744 Method of fabricating a non-SOI device on an SOI starting wafer and thinning the same |
| 05/21/2002 | US6391743 Method and apparatus for producing photoelectric conversion device |
| 05/21/2002 | US6391740 Generic layer transfer methodology by controlled cleavage process |
| 05/21/2002 | US6391739 Process of eliminating a shallow trench isolation divot |
| 05/21/2002 | US6391738 Depositing an oxide layer over a substrate and exposing the deposited oxide layer to a chlorine containing gas effective to getter metals outwardly therefrom |
| 05/21/2002 | US6391737 Method of simultaneously forming patterns on a die of an alignment mark and other dies |
| 05/21/2002 | US6391736 Method for fabricating a capacitor of a semiconductor device and a capacitor made thereby |
| 05/21/2002 | US6391735 Container capacitor structure |
| 05/21/2002 | US6391734 Method of making a resistor, method of making a diode, and SRAM circuitry and other integrated circuitry |
| 05/21/2002 | US6391733 Method of doping semiconductor devices through a layer of dielectric material |
| 05/21/2002 | US6391732 Method to form self-aligned, L-shaped sidewall spacers |
| 05/21/2002 | US6391731 Activating source and drain junctions and extensions using a single laser anneal |
| 05/21/2002 | US6391730 Process for fabricating shallow pocket regions in a non-volatile semiconductor device |
| 05/21/2002 | US6391729 Shallow trench isolation formation to eliminate poly stringer with controlled step height and corner rounding |
| 05/21/2002 | US6391728 Method of forming a highly localized halo profile to prevent punch-through |
| 05/21/2002 | US6391727 Method of manufacturing a semiconductor device utilizing a(Al2O3)X-(TiO2)1-X gate dielectric film |
| 05/21/2002 | US6391726 Method of fabricating integrated circuitry |
| 05/21/2002 | US6391725 Semiconductor device and method for fabricating the same |
| 05/21/2002 | US6391724 Method for manufacturing a gate structure incorporating aluminum oxide as a gate dielectric |
| 05/21/2002 | US6391723 Fabrication of VDMOS structure with reduced parasitic effects |
| 05/21/2002 | US6391722 Method of making nonvolatile memory having high capacitive coupling ratio |
| 05/21/2002 | US6391721 Non-volatile semiconductor memory device having vertical transistors and fabrication method therefor |
| 05/21/2002 | US6391720 Process flow for a performance enhanced MOSFET with self-aligned, recessed channel |
| 05/21/2002 | US6391719 Method of manufacture of vertical split gate flash memory device |
| 05/21/2002 | US6391718 Planarization method for flash memory device |
| 05/21/2002 | US6391717 Method of manufacturing a flash memory device |
| 05/21/2002 | US6391716 Method for forming poly spacer electron tunnel oxide flash with electric-field enhancing corners for poly to poly erase |
| 05/21/2002 | US6391715 To prevent operational failure caused by cleaning steps that follow doping ph3 onto hemispherical grain; doping and forming of dielectric layer are performed in a single process chamber without breaking up of a vacuum state of the chamber |
| 05/21/2002 | US6391714 Method for fabricating a capacitor in a semiconductor memory device |
| 05/21/2002 | US6391713 Method for forming a dual damascene structure having capacitors |
| 05/21/2002 | US6391712 Method of forming a storage node of a capacitor that prevents HSG(Hemi-Spherical Grain) bridging |
| 05/21/2002 | US6391711 Method of forming electrical connection between stack capacitor and node location of substrate |
| 05/21/2002 | US6391710 Methods of forming capacitors |
| 05/21/2002 | US6391709 Enhanced capacitor shape |
| 05/21/2002 | US6391708 Method of manufacturing DRAM capacitor |
| 05/21/2002 | US6391707 Method of manufacturing a zero mask high density metal/insulator/metal capacitor |
| 05/21/2002 | US6391706 Method for making deep trench capacitors for DRAMs with reduced faceting at the substrate edge and providing a more uniform pad Si3N4layer across the substrate |
| 05/21/2002 | US6391705 Fabrication method of high-density semiconductor memory cell structure having a trench |
| 05/21/2002 | US6391704 Includes forming a fourth mask layer pattern which exposes parts of the nitride layer of the dram device region, and etching |
| 05/21/2002 | US6391703 Buried strap for DRAM using junction isolation technique |
| 05/21/2002 | US6391702 Method of manufacture for semiconductor devices |
| 05/21/2002 | US6391701 Semiconductor device and process of fabrication thereof |
| 05/21/2002 | US6391700 Method for forming twin-well regions of semiconductor devices |
| 05/21/2002 | US6391699 Method of manufacturing a trench MOSFET using selective growth epitaxy |
| 05/21/2002 | US6391698 Forming complementary metal-oxide semiconductor with gradient doped source/drain |
| 05/21/2002 | US6391697 Method for the formation of gate electrode of semiconductor device using a difference in polishing selection ratio between polymer and oxide film |
| 05/21/2002 | US6391696 Field effect transistor and method of manufacturing thereof |
| 05/21/2002 | US6391695 Double-gate transistor formed in a thermal process |
| 05/21/2002 | US6391694 Manufacturing method of semiconductor integrated circuit |
| 05/21/2002 | US6391693 Method for making polysilicon thin film transistor having multiple gate electrodes |
| 05/21/2002 | US6391692 Method of manufacturing an FET with a second insulation layer covering angular portions of the activation layer |
| 05/21/2002 | US6391691 Method of fabricating a thin film transistor with metal source and drain electrodes by diffusing impurities from a semiconductor layer |
| 05/21/2002 | US6391690 Thin film semiconductor device and method for producing the same |
| 05/21/2002 | US6391689 Method of forming a self-aligned thyristor |
| 05/21/2002 | US6391687 Column ball grid array package |
| 05/21/2002 | US6391686 Adhesive material applying method and apparatus, interconnect substrate, semiconductor device and manufacturing method thereof, circuit board and electronic instrument |
| 05/21/2002 | US6391685 Method of forming through-holes in a wafer and then dicing to form stacked semiconductor devices |
| 05/21/2002 | US6391684 Lead frame and manufacturing method thereof |
| 05/21/2002 | US6391683 Flip-chip semiconductor package structure and process for fabricating the same |
| 05/21/2002 | US6391682 Method of performing flip-chip underfill in a wire-bonded chip-on-chip ball-grid array integrated circuit package module |
| 05/21/2002 | US6391681 Semiconductor component having selected terminal contacts with multiple electrical paths |
| 05/21/2002 | US6391679 Method of processing a single semiconductor using at least one carrier element |
| 05/21/2002 | US6391674 Process for fabricating single crystal resonant devices that are compatible with integrated circuit processing |
| 05/21/2002 | US6391668 Method of determining a trap density of a semiconductor/oxide interface by a contactless charge technique |
| 05/21/2002 | US6391665 Method of monitoring a source contact in a flash memory |
| 05/21/2002 | US6391664 Selectively activatable solar cells for integrated circuit analysis |
| 05/21/2002 | US6391661 Semiconductor and method of fabricating |
| 05/21/2002 | US6391660 Method for fabricating semiconductor memory device having ferroelectric layer |
| 05/21/2002 | US6391659 Methods for fabricating ferroelectric memory devices using pulsed-power plasma |
| 05/21/2002 | US6391658 Such as magnetorestive memory elements and fet, including dual-gate field effect transistors; wafer bonding process to place a single crystal si diode atop the conducting via |
| 05/21/2002 | US6391525 Forming template mask comprising silicon oxynitride, nitride, photoresist or low k polymer; etching; high resolution photolithography; microelectronics, semiconductors |
| 05/21/2002 | US6391521 Resist compositions containing bulky anhydride additives |
| 05/21/2002 | US6391520 Compounds for photoresist and resin composition for photoresist |
| 05/21/2002 | US6391514 Film forming resin, photosensitizer; and alkylene glycol alkyl ether, alkyl amyl ketone, and/or alkyl alkoxy propionate; coating onto silicon wafer; exposure, development, imaging; resolution |
| 05/21/2002 | US6391513 Positively photosensitive resin composition |
| 05/21/2002 | US6391501 Pattern generating method and apparatus |
| 05/21/2002 | US6391500 Border portion between transparent and opaque portions includes some coated patterned structures; smoothness, roundness; photolithography |
| 05/21/2002 | US6391472 Polymer binder and a solvent system for the solid components |
| 05/21/2002 | US6391437 Composite material and manufacturing method thereof, substrate processing apparatus and manufacturing method thereof, substrate mounting stage and manufacturing method thereof, and substrate processing method |
| 05/21/2002 | US6391426 High capacitance storage node structures |
| 05/21/2002 | US6391422 Wiring substrate and stiffener therefor |
| 05/21/2002 | US6391395 Method of fabricating a polysilicon layer |
| 05/21/2002 | US6391377 Surface treating; controlling timing of process with freely programmable process controller unit |
| 05/21/2002 | US6391217 Methods and apparatus for forming submicron patterns on films |
| 05/21/2002 | US6391171 Flangeless feed through |
| 05/21/2002 | US6391166 Plating apparatus and method |
| 05/21/2002 | US6391163 Method of enhancing hardness of sputter deposited copper films |
| 05/21/2002 | US6391148 Etching the silicide layer at a temperature higher than that used to etch the rest of layers to accomplish anisotropic etch; carried out in an apparatus designed for handling silicide films |
| 05/21/2002 | US6391145 Solar cells and semiconductors and etching a silicon substrates and dipping in acid |
| 05/21/2002 | US6391119 Cleaning metal oxide films with acid etching and immersion |
| 05/21/2002 | US6391118 Method for removing particles from surface of article |