Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2002
05/14/2002US6388341 Semiconductor device
05/14/2002US6388340 Compliant semiconductor chip package with fan-out leads and method of making same
05/14/2002US6388339 Sealed-by-resin type semiconductor device and liquid crystal display module including the same
05/14/2002US6388338 Plastic package for an integrated electronic semiconductor device
05/14/2002US6388337 Post-processing a completed semiconductor device
05/14/2002US6388334 System and method for circuit rebuilding via backside access
05/14/2002US6388333 Semiconductor device having protruding electrodes higher than a sealed portion
05/14/2002US6388332 Integrated circuit power and ground routing
05/14/2002US6388330 Low dielectric constant etch stop layers in integrated circuit interconnects
05/14/2002US6388329 Semiconductor integrated circuit having three wiring layers
05/14/2002US6388328 Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system
05/14/2002US6388327 Capping layer for improved silicide formation in narrow semiconductor structures
05/14/2002US6388326 Bonding pad on a semiconductor chip
05/14/2002US6388325 Multi-layer interconnect
05/14/2002US6388322 Article comprising a mechanically compliant bump
05/14/2002US6388321 Anisotropic conductive film and resin filling gap between a flip-chip and circuit board
05/14/2002US6388318 Surface mount-type package of ball grid array with multi-chip mounting
05/14/2002US6388309 Apparatus and method for manufacturing semiconductors using low dielectric constant materials
05/14/2002US6388308 Semiconductor device and method for driving the same
05/14/2002US6388307 Bipolar transistor
05/14/2002US6388306 Semiconductor device with rapid reverse recovery characteristic
05/14/2002US6388305 Electrically programmable antifuses and methods for forming the same
05/14/2002US6388304 Semiconductor device having buried-type element isolation structure and method of manufacturing the same
05/14/2002US6388303 Semiconductor device and semiconductor device manufacture method
05/14/2002US6388300 Semiconductor physical quantity sensor and method of manufacturing the same
05/14/2002US6388298 Detached drain MOSFET
05/14/2002US6388297 Structure and method for an optical block in shallow trench isolation for improved laser anneal control
05/14/2002US6388296 CMOS self-aligned strapped interconnection
05/14/2002US6388295 Semiconductor device and method of manufacturing the same
05/14/2002US6388294 Integrated circuit using damascene gate structure
05/14/2002US6388293 Nonvolatile memory cell, operating method of the same and nonvolatile memory array
05/14/2002US6388291 Semiconductor integrated circuit and method for forming the same
05/14/2002US6388290 Single crystal silicon on polycrystalline silicon integrated circuits
05/14/2002US6388288 Integrating dual supply voltages using a single extra mask level
05/14/2002US6388287 Switch mode power supply with reduced switching losses
05/14/2002US6388286 Power semiconductor devices having trench-based gate electrodes and field plates
05/14/2002US6388285 Feram cell with internal oxygen source and method of oxygen release
05/14/2002US6388284 Capacitor structures
05/14/2002US6388282 Semiconductor memory device and method of manufacture the same
05/14/2002US6388281 Triple metal line 1T/1C ferroelectric memory device and method for fabrication thereof
05/14/2002US6388278 Solid state image pickup device and its driving method
05/14/2002US6388277 Auto placement and routing device and semiconductor integrated circuit
05/14/2002US6388276 Reverse conducting thyristor
05/14/2002US6388275 Compound semiconductor device based on gallium nitride
05/14/2002US6388273 Substrate material for mounting a semiconductor device, substrate for mounting a semiconductor device, semiconductor device, and method of producing the same
05/14/2002US6388272 A sic semiconductor device in which the third conductive layer comprises one of an os layer and a tac/wc/w layer.
05/14/2002US6388271 Semiconductor component
05/14/2002US6388270 Semiconductors with germanium silicides layers
05/14/2002US6388269 Metal interconnection structure for evaluation on electromigration
05/14/2002US6388263 Vacuum system with mist prevention apparatus for manufacturing semiconductor devices and method using the same
05/14/2002US6388261 Charged-particle-beam microlithography apparatus and methods exhibiting reduced astigmatisms and linear distortion
05/14/2002US6388253 Integrated critical dimension control for semiconductor device manufacturing
05/14/2002US6388230 Laser imaging of thin layer electronic circuitry material
05/14/2002US6388203 Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
05/14/2002US6388198 Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality
05/14/2002US6388101 Methacrylic acid ester of 3-hydroxy-3-methyl-1-oxacyclopentan-2-one
05/14/2002US6388039 Acrylated resin
05/14/2002US6388037 Allylated amide compounds and die attach adhesives prepared therefrom
05/14/2002US6387859 Method and cleaner composition for stripping copper containing residue layers
05/14/2002US6387851 Strontium titanate
05/14/2002US6387829 Separation process for silicon-on-insulator wafer fabrication
05/14/2002US6387828 High-pressure anneal process for integrated circuits
05/14/2002US6387827 Thermal oxidation
05/14/2002US6387825 Solution flow-in for uniform deposition of spin-on films
05/14/2002US6387824 Method for forming porous forming film wiring structure
05/14/2002US6387823 Method and apparatus for controlling deposition process using residual gas analysis
05/14/2002US6387822 Application of an ozonated DI water spray to resist residue removal processes
05/14/2002US6387821 Forming, on a semiconductor substrate wiring made of cupper or its alloy; forming insulating film on wiring; forming via hole by dry etching; removing contaminanats by using cleaning solution containing complexing agent; forming a barrier metal
05/14/2002US6387820 BC13/AR chemistry for metal overetching on a high density plasma etcher
05/14/2002US6387819 Method for etching low K dielectric layers
05/14/2002US6387818 Method of porous dielectric formation with anodic template
05/14/2002US6387817 Plasma confinement shield
05/14/2002US6387816 Method and apparatus for controlling the temperature of a gas distribution plate in a process reactor
05/14/2002US6387815 Method of manufacturing semiconductor substrate
05/14/2002US6387814 Method of fabricating a stringerless flash memory
05/14/2002US6387813 Using oxygen plasma; immersion in hydrogen fluoride
05/14/2002US6387812 Ultrasonic processing of chemical mechanical polishing slurries
05/14/2002US6387811 Method for detecting scratch of an insulating film
05/14/2002US6387810 Disposing a photoresist structure over the substrate; and planarizing the photoresist such as by chemical mechanical polishing to uniform thickness, anisotropic etching partially removes photoresist to create uniform recesses
05/14/2002US6387809 A small amount of single-side lapping is repeated alternately on the two surfaces of a semiconductor silicon single crystal wafer to get to a predetermined total lapping stock removal
05/14/2002US6387808 Method of correcting topographical effects on a micro-electronic substrate
05/14/2002US6387807 Method for selective removal of copper
05/14/2002US6387806 Filling an interconnect opening with different types of alloys to enhance interconnect reliability
05/14/2002US6387805 Copper alloy seed layer for copper metallization
05/14/2002US6387804 Multilayer; gate electrode overcoating semiconductor substrate; forming sidewall spacers; contacting with ozone
05/14/2002US6387803 Method for forming a silicide region on a silicon body
05/14/2002US6387802 Memory capacitor; vapor deposition
05/14/2002US6387801 Method and an apparatus to electroless plate a metal layer while eliminating the photoelectric effect
05/14/2002US6387800 Method of forming barrier and seed layers for electrochemical deposition of copper
05/14/2002US6387799 Method for fabricating titanium silicide film
05/14/2002US6387798 Method of etching trenches for metallization of integrated circuit devices with a narrower width than the design mask profile
05/14/2002US6387797 Method for reducing the capacitance between interconnects by forming voids in dielectric material
05/14/2002US6387796 Semiconductor device and method of manufacturing the same
05/14/2002US6387795 Wafer-level packaging
05/14/2002US6387794 Electrode structure for semiconductor device, method for forming the same, mounted body including semiconductor device and semiconductor device
05/14/2002US6387793 Metallization; applying solder bumps; heating
05/14/2002US6387791 Forming shallow channel, overcoating with photoresist, removal, polishing
05/14/2002US6387790 Forming crystalline liner
05/14/2002US6387789 Method for fabricating semiconductor device
05/14/2002US6387788 Method for forming polycide gate electrode of metal oxide semiconductor field effect transistor