Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2002
08/06/2002US6429501 Semiconductor device having high breakdown voltage and method for manufacturing the device
08/06/2002US6429500 Semiconductor pin diode for high frequency applications
08/06/2002US6429499 Method and apparatus for a monolithic integrated MESFET and p-i-n optical receiver
08/06/2002US6429497 Method for improving breakdown voltage in magnetic tunnel junctions
08/06/2002US6429496 Ion-assisted oxidation methods and the resulting structures
08/06/2002US6429495 Semiconductor device with address programming circuit
08/06/2002US6429494 Semiconductor read-only memory and method of manufacturing the same
08/06/2002US6429493 Semiconductor device and method for manufacturing semiconductor device
08/06/2002US6429490 Protection device and protection method for semiconductor device
08/06/2002US6429488 Densely patterned silicon-on-insulator (SOI) region on a wafer
08/06/2002US6429487 Semiconductor device having gate to body connection
08/06/2002US6429486 Semiconductor support substrate potential fixing structure for SOI semiconductor device
08/06/2002US6429485 Thin film transistor and method of fabricating thereof
08/06/2002US6429484 Multiple active layer structure and a method of making such a structure
08/06/2002US6429483 Semiconductor device and method for forming the same
08/06/2002US6429482 Halo-free non-rectifying contact on chip with halo source/drain diffusion
08/06/2002US6429481 Field effect transistor and method of its manufacture
08/06/2002US6429480 Semiconductor device having nonvolatile memory cell and field effect transistor
08/06/2002US6429479 Nand flash memory with specified gate oxide thickness
08/06/2002US6429478 Semiconductor device which increases the capacity of a capacitor without deepening the contact hole
08/06/2002US6429477 Shared body and diffusion contact structure and method for fabricating same
08/06/2002US6429476 Semiconductor integrated circuit device
08/06/2002US6429475 Cell capacitors, memory cells, memory arrays, and method of fabrication
08/06/2002US6429474 Storage-capacitor electrode and interconnect
08/06/2002US6429473 DRAM cell with stacked capacitor self-aligned to bitline
08/06/2002US6429472 Split gate type flash memory
08/06/2002US6429471 Compound semiconductor field effect transistor and method for the fabrication thereof
08/06/2002US6429470 CMOS imager with storage capacitor
08/06/2002US6429467 Group 3 nitride
08/06/2002US6429466 Integrated circuit substrate that accommodates lattice mismatch stress
08/06/2002US6429465 Crystal structure
08/06/2002US6429459 Semiconductor component with foreign atoms introduced by ion implantation and process for producing the same
08/06/2002US6429457 Field-effect transistor
08/06/2002US6429456 Thin-film transistor elements and methods of making same
08/06/2002US6429455 Method to enhance the formation of nucleation sites on silicon structures and an improved silicon structure
08/06/2002US6429454 Semiconductor device with test circuit
08/06/2002US6429453 Substrate assembly for burn in test of integrated circuit chip
08/06/2002US6429452 Test structure and methodology for characterizing ion implantation in an integrated circuit fabrication process
08/06/2002US6429445 Electron beam irradiating apparatus having cathode plate formed of non-metal conductive material
08/06/2002US6429442 Ion implanter
08/06/2002US6429441 Charged-particle-beam microlithography apparatus and methods exhibiting variable beam velocity, and device-manufacturing methods using same
08/06/2002US6429440 Lithography apparatus having a dynamically variable illumination beam
08/06/2002US6429425 Method for forming a calibation standard to adjust a micro-bar of an electron microscope
08/06/2002US6429399 Discharge tube for a local etching apparatus and a local etching apparatus using the discharge tube
08/06/2002US6429389 Via-in-pad apparatus and methods
08/06/2002US6429384 Chip C4 assembly improvement using magnetic force and adhesive
08/06/2002US6429382 Electrical mounting structure having an elution preventive film
08/06/2002US6429372 Semiconductor device of surface mounting type and method for fabricating the same
08/06/2002US6429325 B-diketonatocopper (ii) complex liquid at room temperature
08/06/2002US6429318 Metal halide layer and hydrogen halide salt of organic diamine are contacted; salt formation, supersaturation, precipitation
08/06/2002US6429238 Liquid epoxy resin and modified polyethersiloxane cured with imidazole-derived cure accelerator; sealing material for flip-chip semiconductor devices; improved thin-film infiltration and storage stability; no need to clean flux
08/06/2002US6429152 Method of forming a thin film on a semiconductor wafer
08/06/2002US6429151 Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers
08/06/2002US6429149 Low temperature LPCVD PSG/BPSG process
08/06/2002US6429148 Anisotropic formation process of oxide layers for vertical transistors
08/06/2002US6429147 Method for making an insulating film
08/06/2002US6429146 Epoxy layer is first covered with a layer of a cover material before the pressing takes place, and the cover is transparent polytetrafluoroethylene or fluorinated ethylene-propylene which allows easy removal of pressed substrate
08/06/2002US6429145 Method of determining electrical properties of silicon-on-insulator wafers
08/06/2002US6429144 Replacing contaminated oxide with relatively pure oxide; pretreating with aqueous solution of hydrogen peroxide and ammonium hydroxide and rinsing to oxidize and remove organic materials and metal contaminants; improved calcium removal
08/06/2002US6429143 Pattern formation method
08/06/2002US6429142 In-situ photoresist removal by an attachable chamber with light source
08/06/2002US6429140 Method of etching of photoresist layer
08/06/2002US6429139 Serial wafer handling mechanism
08/06/2002US6429138 Method of manufacturing semiconductor device
08/06/2002US6429137 Solid state thermal switch
08/06/2002US6429136 Method for forming a shallow trench isolation structure in a semiconductor device
08/06/2002US6429135 Method of reducing stress between a nitride silicon spacer and a substrate
08/06/2002US6429134 Method of manufacturing semiconductor device
08/06/2002US6429133 Composition compatible with aluminum planarization and methods therefore
08/06/2002US6429132 Combination CMP-etch method for forming a thin planar layer over the surface of a device
08/06/2002US6429131 CMP uniformity
08/06/2002US6429130 Method and apparatus for end point detection in a chemical mechanical polishing process using two laser beams
08/06/2002US6429129 Incorporating fluorinated amorphous carbon and fluorocarbon polymers in formation of interconnects; blocking diffusion of fluorine
08/06/2002US6429128 Method of forming nitride capped Cu lines with reduced electromigration along the Cu/nitride interface
08/06/2002US6429127 Fabrication of integrated circuits with ruthenium and/or ruthenium oxide conductive layers; increasing capacitance of lower electrode structure without increasing occupation area of capacitor
08/06/2002US6429126 Reduced fluorine contamination for tungsten CVD
08/06/2002US6429125 Microelectronic device fabricating method
08/06/2002US6429124 Local interconnect structures for integrated circuits and methods for making the same
08/06/2002US6429123 Method of manufacturing buried metal lines having ultra fine features
08/06/2002US6429122 Non metallic barrier formations for copper damascene type interconnects
08/06/2002US6429121 Method of fabricating dual damascene with silicon carbide via mask/ARC
08/06/2002US6429120 Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals
08/06/2002US6429119 Dual damascene process to reduce etch barrier thickness
08/06/2002US6429118 Elimination of electrochemical deposition copper line damage for damascene processing
08/06/2002US6429117 Method to create copper traps by modifying treatment on the dielectrics surface
08/06/2002US6429116 Depositing a diffusion barrier/etch stop layer over a conductive layer, then depositing an organic low k dielectric material thereon; etching and depositing an inorganic low k dielectric in the slot via; slot via wider than the trench
08/06/2002US6429115 Preventing electromigration of copper; enhanced wetting ability on surface of under layer
08/06/2002US6429114 Method for fabricating a multilayer ceramic substrate
08/06/2002US6429113 Method for connecting an electrical device to a circuit substrate
08/06/2002US6429112 Multi-layer substrates and fabrication processes
08/06/2002US6429111 Comprising a p-type aluminum gallium indium nitride semiconductor layer and an electrode layer formed on the semiconductor layer, wherein the electrode layer contains a mixture of a metal nitride and a metal hydride
08/06/2002US6429110 MOSFET with both elevated source-drain and metal gate and fabricating method
08/06/2002US6429109 Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate
08/06/2002US6429108 Non-volatile memory device with encapsulated tungsten gate and method of making same
08/06/2002US6429107 Method for forming conductive contact of semiconductor device
08/06/2002US6429106 Method of automatically defining a landing via
08/06/2002US6429105 Forming metal such as copper interconnect line using chemical mechanical polishing; film forming tetraethylorthosilicate and noble gas impregnated fluorosilicate glass layers; reducing interface and wiring resistance
08/06/2002US6429104 Method for forming cavities in a semiconductor substrate by implanting atoms
08/06/2002US6429103 MOCVD-grown emode HIGFET buffer
08/06/2002US6429102 Method of manufacturing low resistivity p-type compound semiconductor material