Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2002
11/05/2002US6476331 Printed circuit board for semiconductor package and method for manufacturing the same
11/05/2002US6475971 Azeotrope-like composition of 1,2-dichloro-3,3,3-trifluoropropene and hydrogen fluoride composition
11/05/2002US6475966 Plasma etching residue removal
11/05/2002US6475931 Method for producing devices having piezoelectric films
11/05/2002US6475930 UV cure process and tool for low k film formation
11/05/2002US6475929 Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant
11/05/2002US6475928 Process for depositing a Ta2O5 dielectric layer
11/05/2002US6475927 Method of forming a semiconductor device
11/05/2002US6475926 Substrate for high frequency integrated circuits
11/05/2002US6475925 Reduced water adsorption for interlayer dielectric
11/05/2002US6475924 Substrate and process for producing the same
11/05/2002US6475923 Group III nitride compound semiconductor thin film and deposition method thereof, and semiconductor device and manufacturing method thereof
11/05/2002US6475922 Hard mask process to control etch profiles in a gate stack
11/05/2002US6475921 Mask for producing rectangular openings in a substrate
11/05/2002US6475920 Plasma etching method using low ionization potential gas
11/05/2002US6475919 Method for producing trenches for DRAM cell configurations
11/05/2002US6475918 Plasma treatment apparatus and plasma treatment method
11/05/2002US6475917 Method to reduce the metal TiN ARC damage in etching back process
11/05/2002US6475916 Method of patterning gate electrode with ultra-thin gate dielectric
11/05/2002US6475915 Ono etch using CL2/HE chemistry
11/05/2002US6475914 Method of manufacturing semiconductor device for protecting Cu layer from post chemical mechanical polishing-corrosion
11/05/2002US6475913 Method for forming damascene type of metal wires in semiconductor devices
11/05/2002US6475912 Semiconductor device and method and apparatus for fabricating the same while minimizing operating failures and optimizing yield
11/05/2002US6475911 Method of forming noble metal pattern
11/05/2002US6475910 Radical-assisted sequential CVD
11/05/2002US6475909 Method of fabricating metal wiring on a semiconductor substrate using ammonia-containing plating and etching solutions
11/05/2002US6475908 Dual metal gate process: metals and their silicides
11/05/2002US6475907 Semiconductor device having a barrier metal layer and method for manufacturing the same
11/05/2002US6475906 Gate contact etch sequence and plasma doping method for sub-150 NM DT-based DRAM devices
11/05/2002US6475905 Optimization of organic bottom anti-reflective coating (BARC) thickness for dual damascene process
11/05/2002US6475904 Interconnect structure with silicon containing alicyclic polymers and low-k dielectric materials and method of making same with single and dual damascene techniques
11/05/2002US6475903 Copper reflow process
11/05/2002US6475902 Chemical vapor deposition of niobium barriers for copper metallization
11/05/2002US6475901 Method for manufacturing semiconductor device having a multi-layer interconnection
11/05/2002US6475900 Method for manufacturing a metal interconnection having enhanced filling capability
11/05/2002US6475899 Low capacitance wiring layout and method for making same
11/05/2002US6475898 Method of forming interconnectings in semiconductor devices
11/05/2002US6475897 Semiconductor device and method of forming semiconductor device
11/05/2002US6475896 Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument
11/05/2002US6475895 Semiconductor device having a passivation layer and method for its fabrication
11/05/2002US6475894 Process for fabricating a floating gate of a flash memory in a self-aligned manner
11/05/2002US6475893 Method for improved fabrication of salicide structures
11/05/2002US6475892 Simplified method of patterning polysilicon gate in a semiconductor device
11/05/2002US6475891 Method of forming a pattern for a semiconductor device
11/05/2002US6475890 Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
11/05/2002US6475889 Method of forming vias in silicon carbide and resulting devices and circuits
11/05/2002US6475888 Method for forming ultra-shallow junctions using laser annealing
11/05/2002US6475887 Method of manufacturing semiconductor device
11/05/2002US6475886 Fabrication method of nanocrystals using a focused-ion beam
11/05/2002US6475885 Source/drain formation with sub-amorphizing implantation
11/05/2002US6475884 Devices and methods for addressing optical edge effects in connection with etched trenches
11/05/2002US6475883 Method for forming a barrier layer
11/05/2002US6475882 Method for producing GaN-based compound semiconductor and GaN-based compound semiconductor device
11/05/2002US6475881 Fabrication process of a semiconductor device including a dicing process of a semiconductor wafer
11/05/2002US6475879 Semiconductor wafer, method for processing the same and method for manufacturing semiconductor device
11/05/2002US6475878 Method for singulation of integrated circuit devices
11/05/2002US6475877 Method for aligning die to interconnect metal on flex substrate
11/05/2002US6475876 Process for fabricating a semiconductor component
11/05/2002US6475875 Shallow trench isolation elevation uniformity via insertion of a polysilicon etch layer
11/05/2002US6475874 Damascene NiSi metal gate high-k transistor
11/05/2002US6475873 Method of forming laser trimmable thin-film resistors in a fully planarized integrated circuit technology
11/05/2002US6475872 Polysilicon thin film transistor and method of manufacturing the same
11/05/2002US6475869 Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
11/05/2002US6475868 Oxygen implantation for reduction of junction capacitance in MOS transistors
11/05/2002US6475867 Method of forming integrated circuit features by oxidation of titanium hard mask
11/05/2002US6475866 Method for production of a memory cell arrangement
11/05/2002US6475865 Method of fabricating semiconductor device
11/05/2002US6475864 Method of manufacturing a super-junction semiconductor device with an conductivity type layer
11/05/2002US6475863 Method for fabricating self-aligned gate of flash memory cell
11/05/2002US6475862 Semiconductor device having gate insulating layers different in thickness and material and process for fabrication thereof
11/05/2002US6475861 Semiconductor device and fabrication method thereof
11/05/2002US6475860 Method for manufacturing a ferroelectric random access memory device
11/05/2002US6475859 Plasma doping for DRAM with deep trenches and hemispherical grains
11/05/2002US6475858 Method of manufacturing semiconductor device
11/05/2002US6475857 Method of making a scalable two transistor memory device
11/05/2002US6475856 Capacitors and capacitor forming methods
11/05/2002US6475855 Method of forming integrated circuitry, method of forming a capacitor and method of forming DRAM integrated circuitry
11/05/2002US6475854 Method of forming metal electrodes
11/05/2002US6475853 Stacked semiconductor integrated circuit device and manufacturing method thereof
11/05/2002US6475852 Method of forming field effect transistors and related field effect transistor constructions
11/05/2002US6475851 Circuit for providing isolation of integrated circuit active areas
11/05/2002US6475850 Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits
11/05/2002US6475849 Method for reducing base resistance in a bipolar transistor
11/05/2002US6475848 Polysilicon-edge, low-power, high-frequency bipolar transistor and method of forming the transistor
11/05/2002US6475847 Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer
11/05/2002US6475846 Method of making floating-gate memory-cell array with digital logic transistors
11/05/2002US6475844 Field effect transistor and method of manufacturing same
11/05/2002US6475843 Polysilicon thin film transistor with a self-aligned LDD structure
11/05/2002US6475842 Process for gate oxide side-wall protection from plasma damage to form highly reliable gate dielectrics
11/05/2002US6475841 Transistor with shaped gate electrode and method therefor
11/05/2002US6475840 Semiconductor device and method for manufacturing the same
11/05/2002US6475839 Manufacturing of TFT device by backside laser irradiation
11/05/2002US6475838 Methods for forming decoupling capacitors
11/05/2002US6475836 Semiconductor device and manufacturing method thereof
11/05/2002US6475835 Method for forming thin film transistor
11/05/2002US6475833 Bumpless flip chip assembly with strips and via-fill
11/05/2002US6475830 Flip chip and packaged memory module
11/05/2002US6475829 Semiconductor device and manufacturing method thereof
11/05/2002US6475828 Method of using both a non-filled flux underfill and a filled flux underfill to manufacture a flip-chip
11/05/2002US6475827 Method for making a semiconductor package having improved defect testing and increased production yield
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