Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2002
11/12/2002US6479924 Ferroelectric emitter
11/12/2002US6479905 Full CMOS SRAM cell
11/12/2002US6479904 Semiconductor device with registration accuracy measurement mark
11/12/2002US6479903 Flip chip thermally enhanced ball grid array
11/12/2002US6479902 Semiconductor catalytic layer and atomic layer deposition thereof
11/12/2002US6479899 Semiconductor integrated circuit device and process for manufacturing the same
11/12/2002US6479898 Dielectric treatment in integrated circuit interconnects
11/12/2002US6479897 Semiconductor device having fluorine-added carbon dielectric film and method of fabricating the same
11/12/2002US6479896 Semiconductor device having protective layer
11/12/2002US6479893 Ball-less clip bonding
11/12/2002US6479891 Incorrect-placement preventing directional IC tray for carrying IC packages
11/12/2002US6479888 Semiconductor device and a method of manufacturing the same
11/12/2002US6479885 High voltage device and method
11/12/2002US6479884 Interim oxidation of silsesquioxane dielectric for dual damascene process
11/12/2002US6479882 Current-limiting device
11/12/2002US6479881 Low temperature process for forming intermetal gap-filling insulating layers in silicon wafer integrated circuitry
11/12/2002US6479880 Floating gate isolation device
11/12/2002US6479879 Low defect organic BARC coating in a semiconductor structure
11/12/2002US6479877 Semiconductor device for load drive circuit
11/12/2002US6479876 Vertical power MOSFET
11/12/2002US6479875 Fabrication of semiconductor gettering structures by ion implantation
11/12/2002US6479874 Semiconductor memory device having multilevel memory cell and method of manufacturing the same
11/12/2002US6479873 Semiconductor device with self-aligned contact structure
11/12/2002US6479868 Silicon-on-insulator transistors with asymmetric source/drain junctions formed by angled germanium implantation
11/12/2002US6479867 Thin film transistor
11/12/2002US6479866 SOI device with self-aligned selective damage implant, and method
11/12/2002US6479865 SOI device and method of fabricating the same
11/12/2002US6479864 Semiconductor structure having a plurality of gate stacks
11/12/2002US6479863 Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell
11/12/2002US6479861 Method for forming an etch mask during the manufacture of a semiconductor device
11/12/2002US6479860 Semiconductor memory device
11/12/2002US6479859 Split gate flash memory with multiple self-alignments
11/12/2002US6479858 Method and apparatus for a semiconductor device with adjustable threshold voltage
11/12/2002US6479857 Capacitor having a tantalum lower electrode and method of forming the same
11/12/2002US6479856 Electrode and a capacitor and DRAM containing the same
11/12/2002US6479855 Capacitor and conductive line constructions and semiconductor processing methods of forming capacitors and conductive lines
11/12/2002US6479854 Capacitor/antifuse structure having a barrier-layer electrode and improved barrier layer
11/12/2002US6479853 Semiconductor device and manufacturing method thereof
11/12/2002US6479852 Memory cell having a deep trench capacitor and a vertical channel
11/12/2002US6479851 Memory device with divided bit-line architecture
11/12/2002US6479850 Method for fabricating an integrated circuit capacitor
11/12/2002US6479849 Dielectric capacitor and memory and method of manufacturing the same
11/12/2002US6479848 Magnetic random access memory with write and read circuits using magnetic tunnel junction (MTJ) devices
11/12/2002US6479847 Method for complementary oxide transistor fabrication
11/12/2002US6479844 Modulation doped thyristor and complementary transistor combination for a monolithic optoelectronic integrated circuit
11/12/2002US6479843 Single supply HFET with temperature compensation
11/12/2002US6479839 III-V compounds semiconductor device with an AlxByInzGa1-x-y-zN non continuous quantum dot layer
11/12/2002US6479837 Thin film transistor and liquid crystal display unit
11/12/2002US6479832 Surface height detecting apparatus and exposure apparatus using the same
11/12/2002US6479830 Low-sputter-yield coating for hardware near laser-produced plasma
11/12/2002US6479828 Method and system for icosaborane implantation
11/12/2002US6479821 Thermally induced phase switch for laser thermal processing
11/12/2002US6479801 Temperature measuring method, temperature control method and processing apparatus
11/12/2002US6479763 Conductive paste, conductive structure using the same, electronic part, module, circuit board, method for electrical connection, method for manufacturing circuit board, and method for manufacturing ceramic electronic part
11/12/2002US6479760 Printed wiring board for semiconductor plastic package
11/12/2002US6479757 Method of mounting a plurality of electronic parts on a circuit board
11/12/2002US6479443 Cleaning solution and method for cleaning semiconductor substrates after polishing of copper film
11/12/2002US6479411 Method for forming high quality multiple thickness oxide using high temperature descum
11/12/2002US6479410 Processing method for object to be processed including a pre-coating step to seal fluorine
11/12/2002US6479409 Fabrication of a semiconductor device with an interlayer insulating film formed from a plasma devoid of an oxidizing agent
11/12/2002US6479408 Semiconductor device and method of manufacturing the same
11/12/2002US6479407 Semiconductor device and process for producing the same
11/12/2002US6479405 Method of forming silicon oxide layer in semiconductor manufacturing process using spin-on glass composition and isolation method using the same method
11/12/2002US6479404 Process for fabricating a semiconductor device having a metal oxide or a metal silicate gate dielectric layer
11/12/2002US6479403 Method to pattern polysilicon gates with high-k material gate dielectric
11/12/2002US6479402 Method to improve adhesion of molding compound by providing an oxygen rich film over the top surface of a passivation layer
11/12/2002US6479401 Method of forming a dual-layer anti-reflective coating
11/12/2002US6479400 Manufacturing method of system-on-chip and manufacturing method of semiconductor device
11/12/2002US6479399 Forming conductive line on semiconductor substrate, depositing polysilazane-family spin on glass layer on substrate on which conductive line is formed, baking polysilazane-family spin on glass layer, etching
11/12/2002US6479398 Method of manufacturing an amorphous-silicon thin film transistor
11/12/2002US6479397 Method for forming isolation regions on semiconductor device
11/12/2002US6479396 Dry polymer and oxide veil removal for post etch cleaning
11/12/2002US6479395 Methods for forming openings in a substrate and apparatuses with these openings and methods for creating assemblies with openings
11/12/2002US6479394 Method of low-selective etching of dissimilar materials having interfaces at non-perpendicular angles to the etch propagation direction
11/12/2002US6479393 Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers
11/12/2002US6479392 Fabrication method for semiconductor integrated circuit devices and semiconductor integrated circuit device
11/12/2002US6479391 Method for making a dual damascene interconnect using a multilayer hard mask
11/12/2002US6479390 Method of etching material film formed on semiconductor wafer using surface wave coupled plasma etching apparatus
11/12/2002US6479389 Method of doping copper metallization
11/12/2002US6479388 Methods of forming materials over uneven surface topologies, and methods of forming insulative materials over and between conductive lines
11/12/2002US6479387 Silicon nitride layer semiconductor surface is contacted with a surfactant chemical solution so that the nitride layer and micro-particles bare the same type of charge
11/12/2002US6479386 Process for reducing surface variations for polished wafer
11/12/2002US6479385 Interlevel dielectric composite layer for insulation of polysilicon and metal structures
11/12/2002US6479384 Process for fabricating a semiconductor device
11/12/2002US6479383 Method for selective removal of unreacted metal after silicidation
11/12/2002US6479382 Dual-sided semiconductor chip and method for forming the chip with a conductive path through the chip that connects elements on each side of the chip
11/12/2002US6479381 Process for forming a diffusion-barrier-material nitride film
11/12/2002US6479380 Semiconductor device and manufacturing method thereof
11/12/2002US6479379 Self-aligned etch stop for polycrystalline silicon plugs on a semiconductor device
11/12/2002US6479378 Process for forming electrical interconnects in integrated circuits
11/12/2002US6479377 Method for making semiconductor devices having contact plugs and local interconnects
11/12/2002US6479376 Process improvement for the creation of aluminum contact bumps
11/12/2002US6479375 Method of forming a semiconductor device having a non-peeling electrode pad portion
11/12/2002US6479374 Method of manufacturing interconnection structural body
11/12/2002US6479373 Method of structuring layers with a polysilicon layer and an overlying metal or metal silicide layer using a three step etching process with fluorine, chlorine, bromine containing gases
11/12/2002US6479372 Method for avoiding water marks formed during cleaning after well implantation
11/12/2002US6479371 Method and apparatus for manufacturing three-dimensional photonic crystal structure by fusion bonding the aligned lattice layers formed on wafers
11/12/2002US6479370 Isolated structure and method of fabricating such a structure on a substrate
11/12/2002US6479369 Shallow trench isolation (STI) and method of forming the same
11/12/2002US6479368 Method of manufacturing a semiconductor device having a shallow trench isolating region
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