Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
10/2002
10/29/2002US6472750 Process for realizing an intermediate dielectric layer for enhancing the planarity in semiconductor electronic devices
10/29/2002US6472749 Semiconductor device having a shortened wiring length to reduce the size of a chip
10/29/2002US6472748 System and method for providing MMIC seal
10/29/2002US6472745 Semiconductor device
10/29/2002US6472740 Self-supporting air bridge interconnect structure for integrated circuits
10/29/2002US6472738 Compound semiconductor device
10/29/2002US6472732 BGA package and method for fabricating the same
10/29/2002US6472730 Semiconductor device and method of manufacturing the same
10/29/2002US6472728 Condition sensitive adhesive tape for singulated die transport devices
10/29/2002US6472727 Semiconductor device and manufacturing method thereof
10/29/2002US6472726 Semiconductor device and method of fabrication thereof, semiconductor module, circuit board, and electronic equipment
10/29/2002US6472725 Technique for attaching die to leads
10/29/2002US6472723 Substrate contacts and shielding devices in a semiconductor component
10/29/2002US6472721 Dual damascene interconnect structures that include radio frequency capacitors and inductors
10/29/2002US6472719 Method of manufacturing air gap in multilevel interconnection
10/29/2002US6472718 Semiconductor device
10/29/2002US6472717 Method for fabricating reduced contacts using retardation layers
10/29/2002US6472716 Semiconductor device with a well wherein a scaling down of the layout is achieved
10/29/2002US6472715 Reduced soft error rate (SER) construction for integrated circuit structures
10/29/2002US6472714 Semiconductor device in which memory cells and peripheral circuits are provided on the same circuit
10/29/2002US6472713 Semiconductor device having vertical bipolar transistor
10/29/2002US6472712 Gate width determining layer of a second semiconductor conductivity type formed on the surface of said substrate isolated by pn junction from pair of source/drain layers;
10/29/2002US6472711 Semiconductor substrate and production method thereof
10/29/2002US6472710 Field MOS transistor and semiconductor integrated circuit including the same
10/29/2002US6472709 Trench DMOS transistor structure having a low resistance path to a drain contact located on an upper surface
10/29/2002US6472708 Trench MOSFET with structure having low gate charge
10/29/2002US6472707 Semiconductor memory device
10/29/2002US6472706 Semiconductor device
10/29/2002US6472705 Molecular memory & logic
10/29/2002US6472704 Semiconductor device having contact hole and method of manufacturing the same
10/29/2002US6472703 Semiconductor memory device and method for fabricating the same
10/29/2002US6472702 Deep trench DRAM with SOI and STI
10/29/2002US6472701 Non-volatile semiconductor memory device and its manufacturing method
10/29/2002US6472700 Semiconductor device with isolation insulator, interlayer insulation film, and a sidewall coating film
10/29/2002US6472697 Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application
10/29/2002US6472696 Memory cell configuration and corresponding production process
10/29/2002US6472695 Increased lateral oxidation rate of aluminum indium arsenide
10/29/2002US6472694 High quality epitaxial layers of monocrystalline materials grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers.
10/29/2002US6472686 Silicon carbide (SIC) gate turn-off (GTO) thyristor apparatus and method for high power control
10/29/2002US6472685 Semiconductor device
10/29/2002US6472684 Nonvolatile memory and manufacturing method thereof
10/29/2002US6472680 Semiconductor structures using a group III-nitride quaternary material system with reduced phase separation
10/29/2002US6472679 Semiconductor structures using a group III-nitride quaternary material system with reduced phase separation and method of fabrication
10/29/2002US6472678 Trench MOSFET with double-diffused body profile
10/29/2002US6472674 Electron beam exposure system and method of manufacturing devices using the same
10/29/2002US6472673 Lithographic method for producing an exposure pattern on a substrate
10/29/2002US6472643 Substrate thermal management system
10/29/2002US6472641 Lamp unit for light radiation type heating and processing device
10/29/2002US6472639 Heat treatment method and heat treatment apparatus
10/29/2002US6472608 Semiconductor device
10/29/2002US6472543 Lactone compounds having alicyclic structure and their manufacturing method
10/29/2002US6472337 Precursors for zirconium and hafnium oxide thin film deposition
10/29/2002US6472336 Forming an encapsulating layer after deposition of a dielectric comprised of corrosive material
10/29/2002US6472335 Methods of adhesion promoter between low-K layer and underlying insulating layer
10/29/2002US6472334 Film forming method, semiconductor device manufacturing method, and semiconductor device
10/29/2002US6472333 Silicon carbide cap layers for low dielectric constant silicon oxide layers
10/29/2002US6472332 Surface micromachined structure fabrication methods for a fluid ejection device
10/29/2002US6472331 Method and apparatus for measuring and dispensing a wafer etchant
10/29/2002US6472330 Method for forming an interlayer insulating film, and semiconductor device
10/29/2002US6472329 Etching aluminum over refractory metal with successive plasmas
10/29/2002US6472328 Methods of forming an electrical contact to semiconductive material
10/29/2002US6472327 Method and system for etching tunnel oxide to reduce undercutting during memory array fabrication
10/29/2002US6472326 Reliable particle removal following a process chamber wet clean
10/29/2002US6472325 Method and apparatuses for monitoring and controlling mechanical or chemical-mechanical planarization of microelectronic substrate assemblies
10/29/2002US6472324 Method of manufacturing trench type element isolation structure
10/29/2002US6472323 Method of depositing tungsten nitride using a source gas comprising silicon
10/29/2002US6472322 Method of forming a metal to polysilicon contact in oxygen environment
10/29/2002US6472321 Chemical vapor deposition process
10/29/2002US6472320 Method of producing rough polysilicon by the use of pulsed plasma chemical vapor deposition and products produced by the same
10/29/2002US6472319 Forming an upper electrode of a noble metal over dielctric layer on a lower electrode, performing first heat treatment at a lower temperature than oxidation temperature of noble metal with oxygen, then second heat treatment without oxygen
10/29/2002US6472318 Method of fabricating semiconductor device having trench interconnection
10/29/2002US6472316 Photolithography overlay control
10/29/2002US6472315 Method of via patterning utilizing hard mask and stripping patterning material at low temperature
10/29/2002US6472314 Diamond barrier layer
10/29/2002US6472313 Semiconductors; heat resistance
10/29/2002US6472312 Methods for inhibiting microelectronic damascene processing induced low dielectric constant dielectric layer physical degradation
10/29/2002US6472311 Method for manufacturing semiconductor device
10/29/2002US6472310 Tin palladium activation with maximized nuclei density and uniformity on barrier material in interconnect structure
10/29/2002US6472309 In situ plasma pre-deposition wafer treatment in chemical vapor deposition technology for semiconductor integrated circuit applications
10/29/2002US6472308 Borderless vias on bottom metal
10/29/2002US6472307 Methods for improved encapsulation of thick metal features in integrated circuit fabrication
10/29/2002US6472306 Method of forming a dual damascene opening using CVD Low-K material and spin-on-polymer
10/29/2002US6472305 Method of manufacturing bonded structure of film substrate and semiconductor chip
10/29/2002US6472304 Wire bonding to copper
10/29/2002US6472303 Method of forming a contact plug for a semiconductor device
10/29/2002US6472302 Integration method for raised contact formation for sub-150 nm devices
10/29/2002US6472301 Method and structure for shallow trench isolation
10/29/2002US6472300 Method for growing p-n homojunction-based structures utilizing HVPE techniques
10/29/2002US6472299 Method and apparatus for treating a substrate with hydrogen radicals at a temperature of less than 40 K
10/29/2002US6472297 Method of producing TFT array substrate for liquid crystal display device
10/29/2002US6472296 Fabrication of photovoltaic cell by plasma process
10/29/2002US6472295 Method and apparatus for laser ablation of a target material
10/29/2002US6472294 Semiconductor processing method for processing discrete pieces of substrate to form electronic devices
10/29/2002US6472293 Method for manufacturing an interconnect structure for stacked semiconductor device
10/29/2002US6472292 Process of manufacturing semiconductor device
10/29/2002US6472290 Isolation in micromachined single crystal silicon using deep trench insulation
10/29/2002US6472289 Dielectrically separated wafer and method of manufacturing the same
10/29/2002US6472288 Method of fabricating bipolar transistors with independent impurity profile on the same chip
10/29/2002US6472287 Manufacturing method of semiconductor with a cleansing agent
10/29/2002US6472286 Bipolar ESD protection structure
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