Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2002
11/14/2002US20020168921 Dicing machine
11/14/2002US20020168879 Generating and accelerating the ions by means of an electric field and radiating an ion flow onto an edge part of semiconductor substrate to clean the edge part of the substrate
11/14/2002US20020168878 Ammonia-free silicon nitride is formed by using a gas mixture of one part silane to 135 parts nitrogen to 100 parts helium and 100 parts hydrogen using chemical vapor deposition
11/14/2002US20020168877 Substrate processing apparatus and method of manufacturing semiconductor device
11/14/2002US20020168876 Contact planarization using nanoporous silica materials
11/14/2002US20020168875 Method for fabricating an ONO layer of an NROM
11/14/2002US20020168874 Methods for pretreating a substrate prior to application of a polymeric coat
11/14/2002US20020168873 Method of forming a semiconductor device
11/14/2002US20020168872 Insulators for high density circuits
11/14/2002US20020168870 Method of forming low dielectric constant insulation film for semiconductor device
11/14/2002US20020168869 Oxide-nitride-oxide (ONO) layer, forming a first oxide on a substrate, rapid thermal nitridation for annealing, forming a nitride layer and forming a second oxide
11/14/2002US20020168868 First and second surfaces with different morphology, adding trisilane to the chamber under chemical vapor depostion, and depositing a silane containing film
11/14/2002US20020168867 Semiconductor processing component having low surface contaminant concentration
11/14/2002US20020168865 Etch of silicon nitride selective to silicon and silicon dioxide useful during the formation of a semiconductor device
11/14/2002US20020168864 Method for semiconductor device fabrication
11/14/2002US20020168863 Exclusion and/or application of the processing fluid by applying while the workpiece and a reactor holding the workpiece are spinning
11/14/2002US20020168862 Operating method of a semiconductor etcher
11/14/2002US20020168861 Process for planarization of flash memory cell
11/14/2002US20020168859 Amorphous-silicon type photosensitive member having an amorphous-carbon surface
11/14/2002US20020168858 Etching gas assistant epitaxial method
11/14/2002US20020168857 Method of manufacturing a semiconductor device
11/14/2002US20020168855 Method of fabricating a MOS device
11/14/2002US20020168854 Prevent formation of reaction by-products at a cooled metal flange, and can allow a maintenance period of an apparatus to become longer
11/14/2002US20020168853 Device including an epitaxial nickel silicide on (100) Si or stable nickel silicide on amorphous Si and a method of fabricating the same
11/14/2002US20020168852 Plated chalcogenide random access memory formed by plating the bottom copper electrode with a conductive silver material
11/14/2002US20020168851 Blocking layer is formed on semiconductor substrate by plasma enhanced chemical vapor deposition, blocking layer in region in which metal silicide contact is to be formed is removed by wet etching. metal is reacted with silicon to form silicide
11/14/2002US20020168850 Forming insulating layer and mask layer on active region, etching exposed field region to form a shallow trench, etching portion of mask layer to form recess
11/14/2002US20020168849 First etching stopper formed on lower conductive layer on semiconductor, first insulating layer formed on first etching stopper, second etching stopper formed on first interlayer, second insulating layer formed, layers etched
11/14/2002US20020168848 Method of fabricating an interconnect structure
11/14/2002US20020168847 Generating remote nitrogen containing plasma and flowing activated nitrogen species from remote site to location of metallic layer where it reacts with metal to form nitride
11/14/2002US20020168846 Plug is formed in hole in first insulating film, second insulating film is deposited on first insulating film and buried interconnect is formed in interconnect groove in second insulating film
11/14/2002US20020168845 Semiconductor copper bond pad surface protection
11/14/2002US20020168844 Reduced crystal defect of the epitaxial layer, improved quality; has a tilt angle of at most 100 seconds
11/14/2002US20020168843 Method of forming high density eeprom cell.
11/14/2002US20020168842 Forming spacers of hard mask material on a gate conductor and utilizing spacers during etching to form notches in gate conductor
11/14/2002US20020168841 Method of creating hydrogen isotope reservoirs in a semiconductor device
11/14/2002US20020168838 Method for performing lithographic process to a multi-layered photoresist layer
11/14/2002US20020168837 Attaching silicon oxide layer on silicon layer by growing or depositing, then attaching sapphire layer to oxide layer using wafer bonding
11/14/2002US20020168836 After film (dopant layer) containing doping elements is formed on surface of substrate a vapor phase synthetic diamond film is formed on dopant layer and dopant layer contains diamond particles which become sources of diamond nuclei
11/14/2002US20020168835 Structure of wirelike quantum dots with good quality is formed in materials having an inconsistency in the lattice constants
11/14/2002US20020168834 Substrate has sequentially stacked buffer oxide layer and mask layer, plurality of trenches with different densities formed in stack of substrate/buffer oxide/mask layers, insulating layer formed over substrate to fill trenches
11/14/2002US20020168833 Manufacturing method of semiconductor device and designing method of semiconductor device
11/14/2002US20020168831 Employing a ceramic capacitor which realizes a low voltage operation
11/14/2002US20020168830 Double sided container process used during the manufacture of a semiconductor device
11/14/2002US20020168829 Method for fabricating a bipolar transistor and method for fabricating an integrated circuit configuration having such a bipolar transistor
11/14/2002US20020168828 Gate oxide is formed on silicon substrate of semiconductor wafer, fluorine ions are doped into gate oxide or silicon substrate, conductive layer is formed on gate oxide, etching process is performed, nitride is formed
11/14/2002US20020168827 Suppressing electric charges generated on substrate and which flow to ground potential through substrate prevents damages to substrate due to charge-up
11/14/2002US20020168826 Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors
11/14/2002US20020168825 Method for etching metal layer on a scale of nanometers
11/14/2002US20020168824 Flash memory cell fabrication sequence
11/14/2002US20020168823 Method for fabricating recessed lightly doped drain field effect transistors
11/14/2002US20020168822 Method of fabricating mask read only memory
11/14/2002US20020168821 Fabrication process for a super-self-aligned trench-gated DMOS with reduced on-resistance
11/14/2002US20020168819 Flash memory with conformal floating gate and the method of making the same
11/14/2002US20020168818 Method to manufacture a split gate P+ EEPROM memory cell
11/14/2002US20020168817 Fabricating ferroelectric memory device
11/14/2002US20020168814 Such as for dry etching, sputtering, plasma chemical vapor deposition, which utilize plasma excited with the use of a VHF or UHF-band high frequency power
11/14/2002US20020168813 Stitch and select implementation in twin MONOS array
11/14/2002US20020168812 The interiors of the cavities of seams or voids that have occurred in a conductive film of interlayer connection plugs or damascene wiring are first dried before forming another overlying film, to prevent peeling or blistering of the film
11/14/2002US20020168811 Method of fabricating an insulating layer
11/14/2002US20020168808 Self-aligned LDD poly-Si thin-film transistor
11/14/2002US20020168807 Pattern of an organic molecular film is formed on a substrate, a solution for forming a thin film applied, and the thin film is selectively formed on the organic molecular film pattern
11/14/2002US20020168806 Automated processing method and system for product wafer and non product wafer, and recording medium in which the method is recorded
11/14/2002US20020168804 Electronic devices comprising thin film transistors
11/14/2002US20020168803 Method for re-forming semiconductor layer in TFT-LCD
11/14/2002US20020168802 SiGe/SOI CMOS and method of making the same
11/14/2002US20020168800 Determinating incline; encapsulation with protective coating
11/14/2002US20020168798 On dielectric substrate; compact, lightweight
11/14/2002US20020168797 Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures
11/14/2002US20020168796 Resin sealing; metal substrate
11/14/2002US20020168795 Monitoring, transmission means encapsulated in one-piece package; integrated circuit
11/14/2002US20020168794 Adhesion; weatherproofing; high frequency plasma vapor deposition
11/14/2002US20020168793 Adhesive filler; bonding multilayer sheets
11/14/2002US20020168791 Suppression of n-type autodoping in low-temperature Si and SiGe epitaxy
11/14/2002US20020168790 Glass transparent substrate; patterned overcoatings; pixel electrode; passivation layer
11/14/2002US20020168789 Method to fabricate flat panel display
11/14/2002US20020168788 Glass transparent substrate; patterned overcoatings; pixel electrode; passivation layer
11/14/2002US20020168787 Irradiating circuit pattern; scattering radiation detects defects
11/14/2002US20020168786 Interface void monitoring in a damascene process
11/14/2002US20020168785 Ferroelectric composite material, method of making same, and memory utilizing same
11/14/2002US20020168591 Rapid thermal oxidation; etching
11/14/2002US20020168590 Method of forming storage nodes in a DRAM
11/14/2002US20020168585 Method of designing photosensitive composition and lithography process
11/14/2002US20020168583 Resolution, sensitivity
11/14/2002US20020168577 Method of crystallizing amorphous silicon
11/14/2002US20020168553 Vapor deposition
11/14/2002US20020168538 Wire-bonding alloy composites
11/14/2002US20020168483 Method for forming film by plasma
11/14/2002US20020168468 Diffusion barrier; protective coatings; reacting titanium nitride with organosilicon compound
11/14/2002US20020168467 Plasma vacuum substrate treatment process and system
11/14/2002US20020168256 Wafer ring supplying and returning apparatus
11/14/2002US20020168251 Self-contained semiconductor device manufacturing equipment having compact arrangement of load-lock and processing chambers
11/14/2002US20020168199 Image forming apparatus having structure for preventing noise and vibration of developing device
11/14/2002US20020168191 Substrate processing system and substrate processing method
11/14/2002US20020168067 Copy protection method and system for a field-programmable gate array
11/14/2002US20020167981 Semiconductor device structure including an optically-active material, device formed using the structure, and method of forming the structure and device
11/14/2002US20020167975 Laser spectral engineering for lithographic process
11/14/2002US20020167847 Semiconductor memory device having test mode
11/14/2002US20020167845 Reducing leakage current in memory cells
11/14/2002US20020167839 Field programmable logic arrays with transistors with vertical gates
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