Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2002
11/21/2002WO2002017362A8 Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors and fabricating such devices
11/21/2002WO2002015252A3 A method for producing a metal film, a thin film device having such metal film and a liquid crystal display device having such thin film device
11/21/2002WO2002001630A3 Hermetic high frequency module and method for producing the same
11/21/2002US20020174409 System and method for analyzing power distribution using static timing analysis
11/21/2002US20020174153 Radio frequency data communications device
11/21/2002US20020174029 Method for collecting semiconductor devices and method for selling and using semiconductor devices
11/21/2002US20020173942 Method and apparatus for design validation of complex IC without using logic simulation
11/21/2002US20020173870 Substrate selector
11/21/2002US20020173868 Scheduling method and program for a substrate processing apparatus
11/21/2002US20020173680 Polymer containing spirocyclic olefin monomers, such as 2,5-dioxo-5',6'-didehydro-spiro(tetrahydrofuran-3,2'-norbornane); forming relief images
11/21/2002US20020173637 Nucleotide sequences coding polypeptide for use in the generation of lysine for use in medicines
11/21/2002US20020173298 Wireless programmable logic devices
11/21/2002US20020173259 Polyvinyl acetal composition roller brush with abrasive outer surface
11/21/2002US20020173255 Chemical mechanical polishing retaining ring
11/21/2002US20020173254 Chemical Mechanical polishing apparatus
11/21/2002US20020173244 Polishing tool and polishing method and apparatus using same
11/21/2002US20020173243 Polishing composition having organic polymer particles
11/21/2002US20020173241 Forming a passivating layer copper oxide for reducing the reaction of the copper metal with the polishing mixtures; reducing the problem of dishing of copper circuits of semiconductor devices
11/21/2002US20020173231 Polishing pad for semiconductor wafer and laminated body for polishing of semiconductor wafer equipped with the same as well as method for polishing of semiconductor wafer
11/21/2002US20020173229 Wafer planarization apparatus
11/21/2002US20020173221 Method and apparatus for two-step polishing
11/21/2002US20020173173 Method of producing anneal wafer and anneal wafer
11/21/2002US20020173172 Method for producing hydrogenated silicon oxycarbide films having low dielectric constant
11/21/2002US20020173170 Supplying saturated solution of raw materials to mixing vessel; stirring; filtration; low temperature
11/21/2002US20020173169 Two-step flourinated-borophosophosilicate glass deposition process
11/21/2002US20020173168 Process for producing dielectric thin films
11/21/2002US20020173167 Methods and apparatus for producing stable low k FSG film for HDP-CVD
11/21/2002US20020173166 Ozone generators; ozone reservoir, storage; cleaning semiconductors
11/21/2002US20020173165 Fabrication of semiconductor materials and devices with controlled electrical conductivity
11/21/2002US20020173164 High speed vapor deposition of dielectric; dry etching patterning
11/21/2002US20020173163 Multilayer; overcoating semiconductor; etching; photolithography
11/21/2002US20020173162 Magnetically enhanced plasma oxide etch using hexafluorobutadiene
11/21/2002US20020173161 Plasma processing method
11/21/2002US20020173160 Plasma etching of organic antireflective coating
11/21/2002US20020173159 Single rie process for mimcap top and bottom plates
11/21/2002US20020173158 Method of improving the interlayer adhesion property of low-k layers in a dual damascene process
11/21/2002US20020173157 Dual damascene method employing composite low dielectric constant dielectric layer having intrinsic etch stop characteristics
11/21/2002US20020173156 Adjustment concentration of ozone dissolved in acid solution; corrosion resistance
11/21/2002US20020173155 Thin-film-transistor-array substrate, thin-film-transistor-array fabrication method, and display device
11/21/2002US20020173154 Method of handling a silicon wafer
11/21/2002US20020173153 Device isolation process flow for ARS system
11/21/2002US20020173152 Method for planarizing barc layer in dual damascene process
11/21/2002US20020173151 Removal photoresist; applying pressure sensitive adhesive; releasing
11/21/2002US20020173150 Using masking pattern; etching using gas mixture containing fluorinated hydrocarbon
11/21/2002US20020173149 Local dry etching method
11/21/2002US20020173148 FIB/RIE method for in-line circuit modification of microelectronic chips containing organic dielectric
11/21/2002US20020173147 Thin film semiconductor device and method for producing the same
11/21/2002US20020173146 Metal plated spring structure
11/21/2002US20020173145 Electrical connection materials and electrical connection method
11/21/2002US20020173144 Method of manufacturing a semiconductor device
11/21/2002US20020173143 Method for forming metal wiring layer of semiconductor device
11/21/2002US20020173142 Etching opening in dielectric; forming barrier
11/21/2002US20020173141 Method for fabricating contact holes in DRAM circuits
11/21/2002US20020173140 Conductor chemical-mechanical polishing in integrated circuit interconnects
11/21/2002US20020173139 Fabricating ferroelectric memory device
11/21/2002US20020173138 Method for manufacturing a semiconductor device
11/21/2002US20020173137 Connecting conductivity connecting layers; electrochemical reduction of oxides
11/21/2002US20020173136 Forming photoresist in aperture overcoating substrate; stacking solder bumps; bonding electrodes
11/21/2002US20020173135 Forming photoresist in aperture overcoating substrate; stacking solder bumps; bonding electrodes
11/21/2002US20020173134 Overcoating semiconductor substrate with contact pads; then passivation layer; forming solder bumps
11/21/2002US20020173133 Overcoating semiconductor with bonding pads; passivation layer; cutting into chips
11/21/2002US20020173131 Connecting like electroconductivity zones
11/21/2002US20020173130 Vapor deposition using silane and dopant gas mixture; overcoating with dielectrics and electrodes; controlling concentration of gas mixture
11/21/2002US20020173129 Metal interconnection with low resistance in a semiconductor device and a method of forming the same
11/21/2002US20020173128 Gate-controlled, graded-extension device for deep sub-micron ultra-high-performance devices
11/21/2002US20020173127 Doped silicon deposition process in resistively heated single wafer chamber
11/21/2002US20020173126 Barium strontium titanate annealing process
11/21/2002US20020173124 Vapor deposition using light source
11/21/2002US20020173123 The ultimate SIMOX
11/21/2002US20020173122 In-situ of dichloroethene and NH3 in an H2O steam based oxidation system to provide a source of chlorine
11/21/2002US20020173121 Process for the production of electric parts
11/21/2002US20020173120 Multilayer structure; polishing surfaces; vertical bonding
11/21/2002US20020173119 Method for manufacturing a silicon wafer
11/21/2002US20020173118 Method for manufacturing buried areas
11/21/2002US20020173117 Semiconductor processing component
11/21/2002US20020173116 Photolithography; vapor deposition
11/21/2002US20020173115 Wet etching; cleaning, planarizing wafer
11/21/2002US20020173114 Patterned SOI by oxygen implantation and annealing
11/21/2002US20020173113 Vapor deposition; doping
11/21/2002US20020173112 Method of forming a capacitor
11/21/2002US20020173111 Multilayer; lower electrode, ferroelectricity film and electrode
11/21/2002US20020173110 Method for fabricating a trench contact to a deep trench capacitor having a polysilicon filling
11/21/2002US20020173108 Forming photoresist on semiconductor substrate; lithography; masking; etching
11/21/2002US20020173107 Overcoating semiconductor with active zones and isolation barriers; electroconductive layer; high density computers
11/21/2002US20020173106 Method for forming variable-K gate dielectric
11/21/2002US20020173105 Controlled doping
11/21/2002US20020173104 Method for preventing gate depletion effects of MOS transistor
11/21/2002US20020173103 Method of manufacturing semiconductor device
11/21/2002US20020173102 Method of forming high density multi-state mask rom cells
11/21/2002US20020173101 Embedded electrically programmable read only memory devices
11/21/2002US20020173100 Process for manufacturing semiconductor memory device and semiconductor memory device
11/21/2002US20020173099 High speed, reduced electrical resistance; miniaturization;photolithography
11/21/2002US20020173097 Fabricating ferroelectric memory device
11/21/2002US20020173096 Semiconductor integrated circuit and method of manufacturing same
11/21/2002US20020173095 Method of making high density semiconductor memory
11/21/2002US20020173094 Filing, covering barrier structure with electroconductive material as contactors with substrate; pattern masking
11/21/2002US20020173093 Disposable spacer and method of forming and using same
11/21/2002US20020173092 Forming devices on a semiconductor substrate
11/21/2002US20020173091 Stripe separation zones
11/21/2002US20020173090 Semiconductor integrated device and electronic equipment
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