Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2002
11/26/2002US6486075 Anisotropic wet etching method
11/26/2002US6486074 Methods of masking and etching a semiconductor substrate, and ion implant lithography methods of processing a semiconductor substrate
11/26/2002US6486073 Method for stripping a photo resist on an aluminum alloy
11/26/2002US6486072 System and method to facilitate removal of defects from a substrate
11/26/2002US6486071 Spherical shaped semiconductor integrated circuit
11/26/2002US6486070 Ultra-high oxide to photoresist selective etch of high-aspect-ratio openings in a low-pressure, high-density plasma
11/26/2002US6486069 Cobalt silicide etch process and apparatus
11/26/2002US6486067 Method for improving the electrical isolation between the contact and gate in a self-aligned contact MOSFET device structure
11/26/2002US6486066 Method of generating integrated circuit feature layout for improved chemical mechanical polishing
11/26/2002US6486065 Method of forming nonvolatile memory device utilizing a hard mask
11/26/2002US6486064 Shallow junction formation
11/26/2002US6486063 Semiconductor device manufacturing method for a copper connection
11/26/2002US6486062 Selective deposition of amorphous silicon for formation of nickel silicide with smooth interface on N-doped substrate
11/26/2002US6486061 Post-deposition treatment to enhance properties of Si-O-C low K films
11/26/2002US6486060 Low resistance semiconductor process and structures
11/26/2002US6486059 Dual damascene process using an oxide liner for a dielectric barrier layer
11/26/2002US6486058 Method of forming a photoresist pattern using WASOOM
11/26/2002US6486057 Process for preparing Cu damascene interconnection
11/26/2002US6486055 Method for forming copper interconnections in semiconductor component using electroless plating system
11/26/2002US6486054 Method to achieve robust solder bump height
11/26/2002US6486053 Semiconductor device and fabricating method therefor
11/26/2002US6486052 Package having terminated plating layer and its manufacturing method
11/26/2002US6486050 Method of manufacturing III-nitride semiconductor devices
11/26/2002US6486049 Method of fabricating semiconductor devices with contact studs formed without major polishing defects
11/26/2002US6486048 Method for fabricating a semiconductor device using conductive oxide and metal layer to silicide source + drain
11/26/2002US6486047 Using an atomic layer deposition tool; provides structures for insulating film of an NDRO-type ferroelectric memory device that has a structure of Metal-film/Ferroelectric-film/Insulating-film/Silicon
11/26/2002US6486046 Method of forming polycrystalline semiconductor film
11/26/2002US6486045 Apparatus and method for forming deposited film
11/26/2002US6486044 Band gap engineering of amorphous Al-Ga-N alloys
11/26/2002US6486043 Method of forming dislocation filter in merged SOI and non-SOI chips
11/26/2002US6486042 Methods of forming compound semiconductor layers using spaced trench arrays and semiconductor substrates formed thereby
11/26/2002US6486041 Method and device for controlled cleaving process
11/26/2002US6486040 Chemical mechanical polishing for forming a shallow trench isolation structure
11/26/2002US6486039 Method of fabricating a trench isolation structure having sidewall oxide layers with different thicknesses
11/26/2002US6486038 Method for and device having STI using partial etch trench bottom liner
11/26/2002US6486037 Control of buried oxide quality in low dose SIMOX
11/26/2002US6486036 Method and apparatus for process control of alignment in dual damascene processes
11/26/2002US6486035 Semiconductor device and method for fabricating the same
11/26/2002US6486034 Method of forming LDMOS device with double N-layering
11/26/2002US6486033 SAC method for embedded DRAM devices
11/26/2002US6486032 Method for fabricating control gate and floating gate of a flash memory cell
11/26/2002US6486031 Method of making an EEPROM cell with asymmetric thin window
11/26/2002US6486030 Methods of forming field effect transistors and integrated circuitry including TiN gate element
11/26/2002US6486029 Integration of an ion implant hard mask structure into a process for fabricating high density memory cells
11/26/2002US6486028 Method of fabricating a nitride read-only-memory cell vertical structure
11/26/2002US6486027 Field programmable logic arrays with vertical transistors
11/26/2002US6486026 Method of forming DRAM circuitry
11/26/2002US6486025 Methods for forming memory cell structures
11/26/2002US6486024 Integrated circuit trench device with a dielectric collar stack, and method of forming thereof
11/26/2002US6486023 Memory device with surface-channel peripheral transistor
11/26/2002US6486022 Method of fabricating capacitors
11/26/2002US6486021 Method for manufacturing a semiconductor device having incorporated therein a high K capacitor dielectric
11/26/2002US6486020 High pressure reoxidation/anneal of high dielectric constant materials
11/26/2002US6486018 Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry
11/26/2002US6486017 Method of reducing substrate coupling for chip inductors by creation of dielectric islands by selective EPI deposition
11/26/2002US6486016 Method for forming self aligned contacts
11/26/2002US6486015 Low temperature carbon rich oxy-nitride for improved RIE selectivity
11/26/2002US6486014 Semiconductor device and method of manufacturing the same
11/26/2002US6486013 Method of manufacturing a semiconductor device having regions of different conductivity types isolated by field oxide
11/26/2002US6486012 Semiconductor device having field effect transistors different in thickness of gate electrodes and process of fabrication thereof
11/26/2002US6486011 JFET structure and manufacture method for low on-resistance and low voltage application
11/26/2002US6486010 Method for manufacturing thin film transistor panel
11/26/2002US6486009 Method of fabricating thin-film transistor
11/26/2002US6486008 Manufacturing method of a thin film on a substrate
11/26/2002US6486007 Method of fabricating a memory cell for a static random access memory
11/26/2002US6486006 Semiconductor chip bonded to a thermal conductive sheet having a filled through hole for electrical connection
11/26/2002US6486005 Semiconductor package and method for fabricating the same
11/26/2002US6486004 Method and apparatus for application of spray adhesive to a leadframe for chip bonding
11/26/2002US6486003 Expandable interposer for a microelectronic package and method therefor
11/26/2002US6486001 Fabricating method of semiconductor device
11/26/2002US6486000 Semiconductor package and fabricating method thereof
11/26/2002US6485999 Wiring arrangements having electrically conductive cross connections and method for producing same
11/26/2002US6485997 Method for manufacturing fringe field switching mode liquid crystal display device
11/26/2002US6485993 Method of making opto-electronic devices using sacrificial devices
11/26/2002US6485990 Feed-forward control of an etch processing tool
11/26/2002US6485989 MRAM sense layer isolation
11/26/2002US6485988 Electroconductive contactors
11/26/2002US6485966 Hybrid microorganism for use in gene therapy
11/26/2002US6485895 Methods for forming line patterns in semiconductor substrates
11/26/2002US6485893 Resist pattern forming method and film forming method
11/26/2002US6485891 Exposure apparatus and method
11/26/2002US6485887 Amplification
11/26/2002US6485870 Charged-particle-beam microlithography masks and methods for manufacturing same
11/26/2002US6485843 Apparatus and method for mounting BGA devices
11/26/2002US6485815 Multi-layered dielectric layer including insulating layer having Si-CH3 bond therein and method for fabricating the same
11/26/2002US6485807 Silicon wafers having controlled distribution of defects, and methods of preparing the same
11/26/2002US6485784 Precursors for the growth of strontium tantalum/niobium oxide films
11/26/2002US6485782 Coating film forming method and coating apparatus
11/26/2002US6485779 Solution for forming ferroelectric film and method for forming ferroelectric film
11/26/2002US6485778 Maintaining a level surface on a pool of adhesive material for applying the adhesive material to the lead fingers by contacting the lead fingers with the pool of adhesive material
11/26/2002US6485654 Method of fabricating self-aligned contacts
11/26/2002US6485619 Connecting the metal film on a wafer and/or a stage to a ground; and forming a metal oxide film on said wafer using the sputtering process while said metal film is being grounded.
11/26/2002US6485618 Integrated copper fill process
11/26/2002US6485617 Sputtering method utilizing an extended plasma region
11/26/2002US6485615 Process of depositing a coating onto a substrate by reactive sputtering
11/26/2002US6485605 High temperature process chamber having improved heat endurance
11/26/2002US6485604 Substrate processing apparatus
11/26/2002US6485603 Method and apparatus for conserving energy within a process chamber
11/26/2002US6485602 Plasma processing apparatus
11/26/2002US6485576 Method for removing coating bead at wafer flat edge
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