H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
12/2002
12/03/2002	US6489558 Conductive cap, electronic component, and method of forming insulating film of conductive cap
12/03/2002	US6489432 Organic anti-reflective coating polymer and preparation thereof
12/03/2002	US6489423 Organic anti-reflective polymer and method for manufacturing thereof
12/03/2002	US6489394 Charged ion cleaning devices and cleaning system
12/03/2002	US6489380 Mixtures of fillers, heterocylic ethers, nitriles, lewis acid catalysts and/or brownsted acids having high flexibility and hermetic sealing, used in semiconductor applications
12/03/2002	US6489255 Low temperature/low dopant oxide glass film
12/03/2002	US6489254 Method of forming pre-metal dielectric film on a semiconductor substrate including first layer of undoped oxide of high ozone:TEOS volume ratio and second layer of low ozone doped BPSG
12/03/2002	US6489253 Method of forming a void-free interlayer dielectric (ILD0) for 0.18-μm flash memory technology and semiconductor device thereby formed
12/03/2002	US6489252 Method of forming a spin-on-glass insulation layer
12/03/2002	US6489251 Method of forming a slope lateral structure
12/03/2002	US6489250 Method for cutting group III nitride semiconductor light emitting element
12/03/2002	US6489249 Elimination/reduction of black silicon in DT etch
12/03/2002	US6489248 Method and apparatus for etch passivating and etching a substrate
12/03/2002	US6489247 Copper etch using HCl and HBR chemistry
12/03/2002	US6489246 Method for manufacturing charge-coupled image sensors
12/03/2002	US6489245 Methods for reducing mask erosion during plasma etching
12/03/2002	US6489243 Method for polishing semiconductor device
12/03/2002	US6489242 Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures
12/03/2002	US6489241 Apparatus and method for surface finishing a silicon film
12/03/2002	US6489240 Method for forming copper interconnects
12/03/2002	US6489239 Method of tungsten chemical vapor deposition and tungsten plug formation
12/03/2002	US6489238 Method to reduce photoresist contamination from silicon carbide films
12/03/2002	US6489237 Method of patterning lines in semiconductor devices
12/03/2002	US6489236 Method for manufacturing a semiconductor device having a silicide layer
12/03/2002	US6489235 Method of forming a metal seed layer for subsequent plating
12/03/2002	US6489234 Method of making a semiconductor device
12/03/2002	US6489233 Nonmetallic barriers protect said interconnects from fluorine out-diffusion from surrounding low-dielectric constant fluorinated dielectric materials
12/03/2002	US6489232 ESD resistant device
12/03/2002	US6489231 Method for forming barrier and seed layer
12/03/2002	US6489230 Integration of low-k SiOF as inter-layer dielectric
12/03/2002	US6489229 Method of forming a semiconductor device having conductive bumps without using gold
12/03/2002	US6489227 Method of etching a polysilicon layer during the stripping of the photoresist shape used as an etch mask to create an opening to an underlying fuse structure
12/03/2002	US6489226 Semiconductor processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random access memory (dram) circuitry
12/03/2002	US6489225 Method for controlling dopant profiles and dopant activation by electron beam processing
12/03/2002	US6489224 Method for engineering the threshold voltage of a device using buried wells
12/03/2002	US6489223 Angled implant process
12/03/2002	US6489222 Method of manufacturing a semiconductor device
12/03/2002	US6489221 High temperature pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates
12/03/2002	US6489220 Method and a system for sealing an epitaxial silicon layer on a substrate
12/03/2002	US6489219 Method of alloying a semiconductor device
12/03/2002	US6489218 Singulation method used in leadless packaging process
12/03/2002	US6489217 Method of forming an integrated circuit on a low loss substrate
12/03/2002	US6489216 Chemical mechanical polish (CMP) planarizing method employing topographic mark preservation
12/03/2002	US6489215 Method of making insulator for electrical structures
12/03/2002	US6489214 Method for forming a capacitor of a semiconductor device
12/03/2002	US6489212 Semiconductor device and method for fabricating the same
12/03/2002	US6489211 Method of manufacturing a semiconductor component
12/03/2002	US6489210 Method for forming dual gate in DRAM embedded with a logic circuit
12/03/2002	US6489209 Manufacturing method of LDD-type MOSFET
12/03/2002	US6489208 Method of forming a laminated structure to enhance metal silicide adhesion on polycrystalline silicon
12/03/2002	US6489207 Method of doping a gate and creating a very shallow source/drain extension and resulting semiconductor
12/03/2002	US6489206 Method for forming self-aligned local-halo metal-oxide-semiconductor device
12/03/2002	US6489205 Semiconductor device and method for manufacturing the same
12/03/2002	US6489204 Save MOS device
12/03/2002	US6489203 Stacked LDD high frequency LDMOSFET
12/03/2002	US6489202 Structure of an embedded channel write-erase flash memory cell and fabricating method thereof
12/03/2002	US6489201 Method for manufacturing a semiconductor device
12/03/2002	US6489200 Capacitor fabrication process for analog flash memory devices
12/03/2002	US6489199 Multiple step methods for forming conformal layers
12/03/2002	US6489198 Semiconductor device and method of manufacturing the same
12/03/2002	US6489197 Semiconductor memory device and method of fabricating the same
12/03/2002	US6489196 Method of forming a capacitor with high capacitance and low voltage coefficient
12/03/2002	US6489195 Method for fabricating DRAM cell using a protection layer
12/03/2002	US6489194 Treating surface to prevent oxygen molecules from being adsorbed
12/03/2002	US6489193 Process for device isolation
12/03/2002	US6489192 Base current reversal SRAM memory cell and method
12/03/2002	US6489191 Method for forming self-aligned channel implants using a gate poly reverse mask
12/03/2002	US6489190 Method of fabricating a high-voltage transistor
12/03/2002	US6489189 Method for manufacturing a semiconductor thin film
12/03/2002	US6489188 Laser annealing system for crystallization of semiconductor layer and method of the same
12/03/2002	US6489185 Protective film for the fabrication of direct build-up layers on an encapsulated die package
12/03/2002	US6489182 Method of fabricating a wire arrayed chip size package
12/03/2002	US6489181 Method of manufacturing a semiconductor device
12/03/2002	US6489180 Flip-chip packaging process utilizing no-flow underfill technique
12/03/2002	US6489178 Method of fabricating a molded package for micromechanical devices
12/03/2002	US6489176 Method of manufacturing array substrate for display device and method of manufacturing display device
12/03/2002	US6489175 Electrically pumped long-wavelength VCSEL and methods of fabrication
12/03/2002	US6489173 Method for determining lead span and planarity of semiconductor devices
12/03/2002	US6489083 Selective sizing of features to compensate for resist thickness variations in semiconductor devices
12/03/2002	US6489080 Positive resist composition
12/03/2002	US6489067 Mask used in reduction projection exposure in photolithography
12/03/2002	US6489066 Mitigation of substrate defects in reflective reticles using sequential coating and annealing
12/03/2002	US6489030 Low dielectric constant films used as copper diffusion barrier
12/03/2002	US6488987 Modified substrate, such as semiconductor wafer, guidance system of apparatus known from jp-10-4079 a; eliminating sealing problems; simpler, lower cost; noncontaminating
12/03/2002	US6488984 Forming barrier and conductive metal layers under an environment shutoff from air; pyrolytic decomposition of such as copper from organometallic compound; low resistance; good adhesion
12/03/2002	US6488863 Plasma etching method
12/03/2002	US6488862 Etched patterned copper features free from etch process residue
12/03/2002	US6488847 Process and equipment for recovering developer from photoresist development waste and reusing it
12/03/2002	US6488823 Stress tunable tantalum and tantalum nitride films
12/03/2002	US6488820 Method and apparatus for reducing migration of conductive material on a component
12/03/2002	US6488807 Magnetic confinement in a plasma reactor having an RF bias electrode
12/03/2002	US6488806 Assembly process for flip chip package having a low stress chip and resulting structure
12/03/2002	US6488803 Radiation-curable heat-peelable pressure-sensitive adhesive sheet and process for producing cut pieces with the same
12/03/2002	US6488795 Multilayered ceramic substrate and method of producing the same
12/03/2002	US6488779 Semiconductor wafer cleaning
12/03/2002	US6488778 Apparatus and method for controlling wafer environment between thermal clean and thermal processing
12/03/2002	US6488776 Method and apparatus for forming insitu boron doped polycrystalline and amorphous silicon films
12/03/2002	US6488775 Semiconductor-manufacturing device
12/03/2002	US6488774 Trap apparatus
12/03/2002	US6488767 High surface quality GaN wafer and method of fabricating same

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