Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2003
05/20/2003US6566258 Bi-layer etch stop for inter-level via
05/20/2003US6566257 Method for producing semiconductor device
05/20/2003US6566256 Dual process semiconductor heterostructures and methods
05/20/2003US6566255 SOI annealing method and SOI manufacturing method
05/20/2003US6566254 Method for forming a silicide film on gate electrodes and diffusion layers of MOS transistors
05/20/2003US6566253 Method of making electrical interconnection for attachment to a substrate
05/20/2003US6566252 Method for simultaneous deposition and sputtering of TEOS and device thereby formed
05/20/2003US6566250 Method for forming a self aligned capping layer
05/20/2003US6566249 Planarized semiconductor interconnect topography and method for polishing a metal layer to form wide interconnect structures
05/20/2003US6566248 Graphoepitaxial conductor cores in integrated circuit interconnects
05/20/2003US6566247 Electronic devices with composite atomic barrier film and process for making same
05/20/2003US6566246 Deposition of conformal copper seed layers by control of barrier layer morphology
05/20/2003US6566245 Method of manufacturing probe unit and probe unit manufactured using this method
05/20/2003US6566244 Process for improving mechanical strength of layers of low k dielectric material
05/20/2003US6566243 Forming dielectric layers from small silicalite crystals bound together with a binder to produce low dielectric constant material
05/20/2003US6566242 Dual damascene copper interconnect to a damascene tungsten wiring level
05/20/2003US6566241 Method of forming metal contact in semiconductor device
05/20/2003US6566240 Semiconductor device and method of forming a semiconductor device
05/20/2003US6566239 Semiconductor device manufacturing method having a step of forming a post terminal on a wiring by electroless plating
05/20/2003US6566238 Metal wire fuse structure with cavity
05/20/2003US6566236 Gate structures with increased etch margin for self-aligned contact and the method of forming the same
05/20/2003US6566235 Process for producing semiconductor member, and process for producing solar cell
05/20/2003US6566234 Semiconductor flip-chip package and method for the fabrication thereof
05/20/2003US6566233 Method for manufacturing bonded wafer
05/20/2003US6566232 Method of fabricating semiconductor device
05/20/2003US6566231 Method of manufacturing high performance semiconductor device with reduced lattice defects in the active region
05/20/2003US6566230 Shallow trench isolation spacer for weff improvement
05/20/2003US6566229 Method of forming an insulating layer in a trench isolation type semiconductor device
05/20/2003US6566228 Trench isolation processes using polysilicon-assisted fill
05/20/2003US6566227 Strap resistance using selective oxidation to cap DT poly before STI etch
05/20/2003US6566226 Semiconductor device and fabrication process thereof, method of forming a device isolation structure
05/20/2003US6566225 Formation method of shallow trench isolation
05/20/2003US6566224 Process for device fabrication
05/20/2003US6566223 High voltage integrated switching devices on a bonded and trenched silicon substrate
05/20/2003US6566222 Methods of forming recessed hemispherical grain silicon capacitor structures
05/20/2003US6566221 Capacitor structure and method for fabricating the same
05/20/2003US6566220 Method for fabricating a semiconductor memory component
05/20/2003US6566219 Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the trench opening
05/20/2003US6566218 Boride-based substrate for growing semiconducting layers thereon and a semiconductor device using the same
05/20/2003US6566217 Manufacturing process for semiconductor device
05/20/2003US6566216 Method of manufacturing a trench transistor
05/20/2003US6566215 Method of fabricating short channel MOS transistors with source/drain extensions
05/20/2003US6566214 Method of making a semiconductor device by annealing a metal layer to form metal silicide and using the metal silicide as a hard mask to pattern a polysilicon layer
05/20/2003US6566213 Method of fabricating multi-thickness silicide device formed by disposable spacers
05/20/2003US6566212 Method of fabricating an integrated circuit with ultra-shallow source/drain extensions
05/20/2003US6566211 Surface modified interconnects
05/20/2003US6566210 Method of improving gate activation by employing atomic oxygen enhanced oxidation
05/20/2003US6566209 Method to form shallow junction transistors while eliminating shorts due to junction spiking
05/20/2003US6566208 Method to form elevated source/drain using poly spacer
05/20/2003US6566207 Semiconductor device fabricating method
05/20/2003US6566206 Semiconductor structure having more usable substrate area and method for forming same
05/20/2003US6566205 Method to neutralize fixed charges in high K dielectric
05/20/2003US6566204 Use of mask shadowing and angled implantation in fabricating asymmetrical field-effect transistors
05/20/2003US6566203 Method for preventing electron secondary injection in a pocket implantation process
05/20/2003US6566202 Integrated circuit having at least two vertical MOS transistors and method for manufacturing same
05/20/2003US6566201 Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion
05/20/2003US6566200 Flash memory array structure and method of forming
05/20/2003US6566199 Method and system for forming film, semiconductor device and fabrication method thereof
05/20/2003US6566198 CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufacture
05/20/2003US6566197 Method for fabricating connection structure between segment transistor and memory cell region of flash memory device
05/20/2003US6566196 Sidewall protection in fabrication of integrated circuits
05/20/2003US6566195 Method and structure for an improved floating gate memory cell
05/20/2003US6566194 Salicided gate for virtual ground arrays
05/20/2003US6566193 Method for producing a cell of a semiconductor memory
05/20/2003US6566192 Method of fabricating a trench capacitor of a memory cell
05/20/2003US6566191 Forming electronic structures having dual dielectric thicknesses and the structure so formed
05/20/2003US6566190 Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices
05/20/2003US6566189 Forming a nitride film on a semiconductor substrate; forming an amorphous Tantalum oxynitride thin film over the nitride film, crystallizing the amorphous tantalum oxynitride thin film and forming gate electrode over tantalum oxynitride film
05/20/2003US6566188 Method of forming contact holes in semiconductor devices and method of forming capacitors using the same
05/20/2003US6566187 DRAM cell system and method for producing same
05/20/2003US6566186 Capacitor with stoichiometrically adjusted dielectric and method of fabricating same
05/20/2003US6566185 Method of manufacturing a plural unit high frequency transistor
05/20/2003US6566184 Process to define N/PMOS poly patterns
05/20/2003US6566183 Method of making a transistor, in particular spacers of the transistor
05/20/2003US6566182 DRAM memory cell for DRAM memory device and method for manufacturing it
05/20/2003US6566181 Process for the fabrication of dual gate structures for CMOS devices
05/20/2003US6566180 Thin film transistor and fabrication method thereof
05/20/2003US6566179 Method of manufacturing a transistor
05/20/2003US6566178 Transistor and associated driving device
05/20/2003US6566177 Silicon-on-insulator vertical array device trench capacitor DRAM
05/20/2003US6566176 SOI device with wrap-around contact to underside of body, and method of making
05/20/2003US6566175 Method of manufacturing gate insulated field effect transistors
05/20/2003US6566174 Thin-film transistor elements and methods of making same
05/20/2003US6566173 Polycrystalline silicon thin film transistor and manufacturing method thereof
05/20/2003US6566172 Method for manufacture of fully self-aligned tri-layer a-Si:H thin film transistors
05/20/2003US6566170 Method for forming a device having a cavity with controlled atmosphere
05/20/2003US6566169 Method and apparatus for local vectorial particle cleaning
05/20/2003US6566168 Semiconductor package having implantable conductive lands and method for manufacturing the same
05/20/2003US6566166 Method of manufacturing a cavity-down plastic ball grid array (CD-PBGA) substrate
05/20/2003US6566165 Method for mounting a semiconductor chip to a semiconductor chip-mounting board
05/20/2003US6566162 Method of producing Cu (In, Ga) (Se, S) 2 semiconductor film
05/20/2003US6566160 Method of forming a color filter
05/20/2003US6566159 Method of manufacturing tandem thin-film solar cell
05/20/2003US6566158 Method of preparing a semiconductor using ion implantation in a SiC layer
05/20/2003US6566157 Alignment marks and method of forming the same
05/20/2003US6566154 Method for manufacturing liquid crystal display device
05/20/2003US6566151 Method of forming a color filter
05/20/2003US6566150 Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step
05/20/2003US6566148 Method of making a ferroelectric memory transistor
05/20/2003US6566147 Method for controlling deposition of dielectric films
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