Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2003
05/27/2003US6570202 Ferroelectric integrated circuit having low sensitivity to hydrogen exposure and method for fabricating same
05/27/2003US6570200 Transistor structure using epitaxial layers and manufacturing method thereof
05/27/2003US6570199 Semiconductor device and method of manufacturing the same
05/27/2003US6570197 Optical device having sensing TGTs and switching TFTs with different active layer thickness
05/27/2003US6570195 Power/ground metallization routing in a semiconductor device
05/27/2003US6570194 Compound semiconductor field effect transistor with improved ohmic contact layer structure and method of forming the same
05/27/2003US6570192 Gallium nitride semiconductor structures including lateral gallium nitride layers
05/27/2003US6570189 Semiconductor device and method of manufacturing the same
05/27/2003US6570184 Thin film transistor and method for manufacturing the same
05/27/2003US6570183 Liquid crystal display for preventing galvanic phenomenon
05/27/2003US6570182 Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof
05/27/2003US6570174 Connecting zones; calibration
05/27/2003US6570171 Ion implanter
05/27/2003US6570169 Apparatus for manufacturing a semiconductor device and a method for manufacturing a semiconductor device
05/27/2003US6570168 Illumination system with a plurality of light sources
05/27/2003US6570166 Operation method of ion source and ion beam irradiation apparatus
05/27/2003US6570157 Multi-pitch and line calibration for mask and wafer CD-SEM system
05/27/2003US6570155 Bi-directional electron beam scanning apparatus
05/27/2003US6570137 System and method for lamp split zone control
05/27/2003US6570134 Uniform heating of wafer; concentric filaments, wafer, mirror, guard ring
05/27/2003US6570101 Lead configurations
05/27/2003US6570029 No-flow reworkable epoxy underfills for flip-chip applications
05/27/2003US6569785 Semiconductor integrated circuit device having internal tensile and internal compression stress
05/27/2003US6569784 Material of photoresist protect oxide
05/27/2003US6569783 Graded composition diffusion barriers for chip wiring applications
05/27/2003US6569782 Insulating layer, semiconductor device and methods for fabricating the same
05/27/2003US6569781 Method of forming an ultra-thin oxide layer on a silicon substrate by implantation of nitrogen through a sacrificial layer and subsequent annealing prior to oxide formation
05/27/2003US6569780 Method for fabricating semiconductor integrated circuit device
05/27/2003US6569778 Method for forming fine pattern in semiconductor device
05/27/2003US6569777 Plasma etching method to form dual damascene with improved via profile
05/27/2003US6569776 Using a first fluorine compound including a carbon atom-carbon atom bond (e.g., octafluorocyclobutane) and a second fluorine compound including at least one hydrogen atom and a single carbon (e.g., CH3F)
05/27/2003US6569775 Method for enhancing plasma processing performance
05/27/2003US6569774 Method to eliminate striations and surface roughness caused by dry etch
05/27/2003US6569773 Method for anisotropic plasma-chemical dry etching of silicon nitride layers using a gas mixture containing fluorine
05/27/2003US6569771 Carrier head for chemical mechanical polishing
05/27/2003US6569770 Method for improving oxide erosion of tungsten CMP operations
05/27/2003US6569769 Slurry-less chemical-mechanical polishing
05/27/2003US6569768 Surface treatment and capping layer process for producing a copper interface in a semiconductor device
05/27/2003US6569767 Semiconductor device and its production process
05/27/2003US6569766 Method for forming a silicide of metal with a high melting point in a semiconductor device
05/27/2003US6569765 Hybrid deposition system and methods
05/27/2003US6569764 Method of manufacturing a semiconductor package by attaching a lead frame to a semiconductor chip via projecting electrodes and an insulating sheet of resin material
05/27/2003US6569763 Method to separate a metal film from an insulating film in a semiconductor device using adhesive tape
05/27/2003US6569761 In semiconductor processes by an over-exposure to a photosensitive layer to form a patterned photosensitive layer on a substrate by using a patterned reticle
05/27/2003US6569760 Method to prevent poison via
05/27/2003US6569759 Semiconductor device having interconnection implemented by refractory metal nitride layer and refractory metal silicide layer and process of fabrication thereof
05/27/2003US6569758 Sub-milliohm on-chip interconnection
05/27/2003US6569757 Methods for forming co-axial interconnect lines in a CMOS process for high speed applications
05/27/2003US6569756 Method for manufacturing a semiconductor device
05/27/2003US6569755 Semiconductor device having an improved structure for preventing cracks, improved small sized semiconductor and method of manufacturing the same
05/27/2003US6569754 Method for making a module including a microplatform
05/27/2003US6569753 Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same
05/27/2003US6569752 Semiconductor element and fabricating method thereof
05/27/2003US6569751 Low via resistance system
05/27/2003US6569750 Method for forming device isolation film for semiconductor device
05/27/2003US6569749 Silicon and oxygen ion co-implanation for metallic gettering in epitaxial wafers
05/27/2003US6569748 Substrate and production method thereof
05/27/2003US6569747 Methods for trench isolation with reduced step height
05/27/2003US6569746 Methods of forming integrated circuit capacitors having electrodes therein that comprise conductive plugs
05/27/2003US6569745 Shared bit line cross point memory array
05/27/2003US6569744 Method of converting a metal oxide semiconductor transistor into a bipolar transistor
05/27/2003US6569743 Method of fabricating a semiconductor device
05/27/2003US6569742 Method of manufacturing semiconductor integrated circuit device having silicide layers
05/27/2003US6569741 Hydrogen anneal before gate oxidation
05/27/2003US6569739 Method of reducing the effect of implantation damage to shallow trench isolation regions during the formation of variable thickness gate layers
05/27/2003US6569738 Process for manufacturing trench gated MOSFET having drain/drift region
05/27/2003US6569737 Method of fabricating a transistor in a semiconductor device
05/27/2003US6569736 Method for fabricating square polysilicon spacers for a split gate flash memory device by multi-step polysilicon etch
05/27/2003US6569735 Manufacturing method for isolation on non-volatile memory
05/27/2003US6569734 Method for two-sided fabrication of a memory array
05/27/2003US6569733 Gate device with raised channel and method
05/27/2003US6569732 Integrated process sequence allowing elimination of polysilicon residue and silicon damage during the fabrication of a buried stack capacitor structure in a SRAM cell
05/27/2003US6569731 Method of forming a capacitor dielectric structure
05/27/2003US6569730 High voltage transistor using P+ buried layer
05/27/2003US6569729 Method of fabricating three dimensional CMOSFET devices for an embedded DRAM application
05/27/2003US6569728 Method for manufacturing a capacitor for use in a semiconductor device
05/27/2003US6569726 Method of manufacturing MOS transistor with fluoride implantation on silicon nitride etching stop layer
05/27/2003US6569725 Thin film transistor array and method for fabricating the same
05/27/2003US6569724 Insulated gate field effect transistor and method for forming the same
05/27/2003US6569723 Crossed strapped VSS layout for full CMOS SRAM cell
05/27/2003US6569721 Method of manufacturing a thin film transistor to reduce contact resistance between a drain region and an interconnecting metal line
05/27/2003US6569720 Method for fabricating thin-film transistor
05/27/2003US6569719 Semiconductor device and method for producing the same
05/27/2003US6569718 Top gate thin-film transistor and method of producing the same
05/27/2003US6569717 Semiconductor device production method, electro-optical device production method, semiconductor device, and electro-optical device
05/27/2003US6569716 Method of manufacturing a polycrystalline silicon film and thin film transistor using lamp and laser anneal
05/27/2003US6569715 Large grain single crystal vertical thin film polysilicon mosfets
05/27/2003US6569714 Method and apparatus for a dense metal programmable ROM
05/27/2003US6569713 Method of fabricating read only memory
05/27/2003US6569711 Methods and apparatus for balancing differences in thermal expansion in electronic packaging
05/27/2003US6569709 Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods
05/27/2003US6569708 Repairable flip chip semiconductor device with excellent packaging reliability and method of manufacturing same
05/27/2003US6569702 Triple layer isolation for silicon microstructure and structures formed using the same
05/27/2003US6569700 Method of reducing leakage current of a photodiode
05/27/2003US6569699 Two layer mirror for LCD-on-silicon products and method of fabrication thereof
05/27/2003US6569696 Device and method for manufacturing semiconductor
05/27/2003US6569695 Method for monitoring particles and defects on wafer surface and in process
05/27/2003US6569693 Method for fabricating epitaxial substrate
05/27/2003US6569691 Measurement of different mobile ion concentrations in the oxide layer of a semiconductor wafer
05/27/2003US6569689 Method of forming a capacitor
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