Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2003
05/28/2003CN1110091C Semiconductor device free from short-circuit between bump electrodes and separation from circuit board and process of fabrication thereof
05/28/2003CN1110089C Semiconductor device
05/28/2003CN1110088C Improved PTFE thin film chip carrier
05/28/2003CN1110087C Clamp assembly for retention of fragile conductive trace with protective clamp
05/28/2003CN1110086C Holder structure of IC package and its manufacture method
05/28/2003CN1110085C Flash memory with separated grid and source injection and its mfg. method
05/28/2003CN1110084C Miniaturized contact in semiconductor substrate and method for forming same
05/28/2003CN1110083C Method for making semiconductor device
05/28/2003CN1110082C Dual damascene process for metal layers and organic intermetal layers
05/28/2003CN1110081C Method for forming isolated channels in semiconductor device
05/28/2003CN1110080C Process for providing metal wire in IC
05/28/2003CN1110079C Electronic part device
05/28/2003CN1110078C Method for mounting semiconductor element
05/28/2003CN1110077C Semiconductor device assembling method and semiconductor device produced by method
05/28/2003CN1110075C Method of fabricating semiconductor device
05/28/2003CN1110074C Method of mfg. semiconductor device
05/28/2003CN1110073C Process for mfg. semiconductor integrated circuit
05/28/2003CN1110072C Method for forming bump electrode of semiconductor device
05/28/2003CN1110071C Method for planarizing semiconductor substrate
05/28/2003CN1110070C Cleaner for large wafer
05/28/2003CN1110069C Apparatus for wet processing semiconductor wafer
05/28/2003CN1110068C Method and device for activating semiconductor impurities
05/28/2003CN1110067C Method of making micro silicon component by utilizing liquid phase epitaxial technique
05/28/2003CN1110066C Semiconductor device mfg. method
05/28/2003CN1110065C Method for making T-shaped grid auto-aligning grid cap to grid foot for semiconductor device
05/28/2003CN1110064C Semiconductor wet processing equipment with emergency output port and method for loading and unloading lots in same
05/28/2003CN1109997C Mask pattern data creation method
05/28/2003CN1109927C Chemically amplified photoresist
05/28/2003CN1109925C 光刻胶组合物 Photoresist composition
05/28/2003CN1109779C Dual vertical thermal treatment furnace
05/28/2003CN1109643C Conveying device and method
05/27/2003US6571384 Method of forming fine patterns on semiconductor device
05/27/2003US6571379 Semiconductor integrated circuit and semiconductor integrated circuit wiring layout method
05/27/2003US6571371 Using latency time between processes for improving wafer-to-wafer uniformity.
05/27/2003US6571183 Imaging using spatial frequency filtering and masking
05/27/2003US6571007 Ball-arranging substrate for forming bump, ball-arranging head, ball-arranging device, and ball-arranging method
05/27/2003US6570812 Semiconductor memory device with improved setup time and hold time
05/27/2003US6570795 Defective memory component of a memory device used to represent a data bit in a bit sequence
05/27/2003US6570792 Bus driving circuit and memory device having same
05/27/2003US6570790 Highly compact EPROM and flash EEPROM devices
05/27/2003US6570788 Semiconductor device and method of driving and method of producing the same
05/27/2003US6570786 NAND-type memory array and method of reading, programming and erasing using the same
05/27/2003US6570783 Asymmetric MRAM cell and bit design for improving bit yield
05/27/2003US6570781 Logic process DRAM
05/27/2003US6570752 Wafer chucks and the like including substrate-adhesion detection and adhesion correction
05/27/2003US6570713 Method and apparatus for optimizing the output beam characteristics of a laser
05/27/2003US6570645 Stage system and stage driving method for use in exposure apparatus
05/27/2003US6570643 Semiconductor device, manufacturing method thereof and semiconductor manufacturing system
05/27/2003US6570630 Display panel
05/27/2003US6570618 Solid-state image sensing apparatus, method for driving the same and camera
05/27/2003US6570552 Semiconductor device and manufacturing method thereof
05/27/2003US6570464 High frequency apparatus
05/27/2003US6570451 High-frequency power amplifier
05/27/2003US6570433 Laser fuseblow protection method for silicon on insulator (SOI) transistors
05/27/2003US6570264 Semiconductor memory device
05/27/2003US6570262 Mother substrate and electronic component utilizing the mother substrate
05/27/2003US6570261 Method and apparatus for injection molded flip chip encapsulation
05/27/2003US6570259 Apparatus to reduce thermal fatigue stress on flip chip solder connections
05/27/2003US6570258 Method for reducing capacitive coupling between conductive lines
05/27/2003US6570257 IMD film composition for dual damascene process
05/27/2003US6570256 Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates
05/27/2003US6570255 A seed layer of a first metal is first deposited into an interconnect opening; the semiconductor structure is then annealed at a temperature sufficient to grow the average grain size in the seed layer to at least the film thickness.
05/27/2003US6570253 Multi-layer film for a thin film structure and a capacitor using the same
05/27/2003US6570252 Integrated circuitry
05/27/2003US6570251 Under bump metalization pad and solder bump connections
05/27/2003US6570245 Stress shield for microelectronic dice
05/27/2003US6570243 At least one of the first dummy interconnect and the second dummy interconnect is connected with at least two of the dummy via holes.
05/27/2003US6570242 Bipolar transistor with high breakdown voltage collector
05/27/2003US6570241 Semiconductor device having the effect that the drop in the current gain is kept to the minimum, when the substrate density is amplified and that the variation in the collector current is improved
05/27/2003US6570240 Semiconductor device having a lateral bipolar transistor and method of manufacturing same
05/27/2003US6570239 Semiconductor device having resistive element
05/27/2003US6570236 Semiconductor device
05/27/2003US6570235 Cells array of mask read only memory
05/27/2003US6570234 Radiation resistant integrated circuit design
05/27/2003US6570233 Processing a bit line contact and a storage node contact used mainly in each element of a dynamic random access memory; reducing the direct contact resistance; and reducing the junction leak while maintaining the punch through margin
05/27/2003US6570232 Local interconnect structure for integrated circuit devices, source structure for the same, and method for fabricating the same
05/27/2003US6570231 Semiconductor device with varying width electrode
05/27/2003US6570229 Semiconductor device
05/27/2003US6570228 Method and apparatus for electrically measuring insulating film thickness
05/27/2003US6570223 Functional device and method of manufacturing the same
05/27/2003US6570222 Solid state imaging device having a photodiode and a MOSFET
05/27/2003US6570221 Bonding of silicon wafers
05/27/2003US6570220 Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition
05/27/2003US6570219 High-voltage transistor with multi-layer conduction region
05/27/2003US6570218 MOSFET with a buried gate
05/27/2003US6570217 To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.
05/27/2003US6570216 EEPROM having a peripheral integrated transistor with thick oxide
05/27/2003US6570215 Spacers increase the capacitive coupling between the floating gate and the control gate
05/27/2003US6570214 Control-gate length and the implanted region are separately defined by two sidewall dielectric spacers formed over a sidewall on the common-source region and, therefore, can be controlled to be smaller
05/27/2003US6570213 Self-aligned split-gate flash memory cell and its contactless NOR-type memory array
05/27/2003US6570212 Complementary avalanche injection EEPROM cell
05/27/2003US6570211 2Bit/cell architecture for floating gate flash memory product and associated method
05/27/2003US6570210 Multilayer pillar array capacitor structure for deep sub-micron CMOS
05/27/2003US6570209 Merged self-aligned source and ONO capacitor for split gate non-volatile memory
05/27/2003US6570208 6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI
05/27/2003US6570207 Can be accessed directly without having to turn on a transfer gate.
05/27/2003US6570206 Semiconductor device
05/27/2003US6570205 DRAM cell
05/27/2003US6570204 Integrated circuitry and DRAM circuitry
05/27/2003US6570203 Semiconductor device and method of manufacturing the same
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