Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2003
05/20/2003US6567258 High temperature electrostatic chuck
05/20/2003US6567257 Method and apparatus for conditioning an electrostatic chuck
05/20/2003US6567219 Laser irradiation apparatus
05/20/2003US6567169 Method of and device for determining the warpage of a wafer
05/20/2003US6567154 Step and scan projection exposure apparatus, maintenance method therefor, and semiconductor device manufacturing method and semiconductor manufacturing factory using the apparatus
05/20/2003US6566937 Fuse circuit
05/20/2003US6566936 Two terminal rectifier normally OFF JFET
05/20/2003US6566931 Semiconductor integrated circuit device with level shift circuit
05/20/2003US6566897 Voltage contrast method and apparatus for semiconductor inspection using low voltage particle beam
05/20/2003US6566896 Semiconductor testing apparatus
05/20/2003US6566888 Repair of resistive electrical connections in an integrated circuit
05/20/2003US6566770 Semiconductor manufacturing apparatus and device manufacturing method
05/20/2003US6566763 Interconnect substrate, apparatus of applying adhesive material, semiconductor device, circuit board and electronic instrument
05/20/2003US6566762 Front side coating for bump devices
05/20/2003US6566759 Self-aligned contact areas for sidewall image transfer formed conductors
05/20/2003US6566756 Semiconductor device with porous interlayer film of a range of average diameter having partially closed holes
05/20/2003US6566755 Method of forming a high surface area interconnection structure
05/20/2003US6566754 Polycrystalline semiconductor device and its manufacture method
05/20/2003US6566753 Composite iridium barrier structure with oxidized refractory metal companion barrier
05/20/2003US6566752 Bonding pad and method for manufacturing it
05/20/2003US6566749 Semiconductor die package with improved thermal and electrical performance
05/20/2003US6566748 Flip-chip semiconductor device having an improved reliability
05/20/2003US6566747 Semiconductor package and production method thereof
05/20/2003US6566741 Grounding of package substrates
05/20/2003US6566740 Lead frame for a semiconductor device and method of manufacturing a semiconductor device
05/20/2003US6566739 Dual chip package
05/20/2003US6566737 Passivation structure for an integrated circuit
05/20/2003US6566735 Integrated circuit chip having anti-moisture-absorption film at edge thereof and method of forming anti-moisture-absorption film
05/20/2003US6566734 Semiconductor device
05/20/2003US6566733 Method and system for providing a power lateral PNP transistor using a buried power buss
05/20/2003US6566732 High voltage resistive structure integrated on a semiconductor substrate
05/20/2003US6566731 Open pattern inductor
05/20/2003US6566729 Semiconductor device including laser-blown links
05/20/2003US6566727 N2O nitrided-oxide trench sidewalls to prevent boron outdiffusion and decrease stress
05/20/2003US6566721 High-accuracy bleeder resistance circuit that can maintain an initial resistance value even after being packaged and can maintain an accurate voltage division ratio.
05/20/2003US6566720 Base cell layout permitting rapid layout with minimum clock line capacitance on CMOS standard-cell and gate-array integrated circuits
05/20/2003US6566719 Semiconductor integrated circuit
05/20/2003US6566718 Field effect transistor with an improved gate contact and method of fabricating the same
05/20/2003US6566717 Integrated circuit with silicided ESD protection transistors
05/20/2003US6566713 Semiconductor device and manufacturing method thereof
05/20/2003US6566712 SOI structure semiconductor device and a fabrication method thereof
05/20/2003US6566711 Semiconductor device having interlayer insulating film
05/20/2003US6566708 Trench-gate field-effect transistors with low gate-drain capacitance and their manufacture
05/20/2003US6566707 Transistor, semiconductor memory and method of fabricating the same
05/20/2003US6566706 Semiconductor array of floating gate memory cells and strap regions
05/20/2003US6566705 Enhanced EPROM structures with accentuated hot electron generation regions
05/20/2003US6566704 Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof
05/20/2003US6566703 High speed flash memory with high coupling ratio
05/20/2003US6566702 Memory cell capacitor utilizes relatively large surface area conductive structures of thin spacer width pillars or having edges without sharp corners that lead to electric field breakdown
05/20/2003US6566701 Microelectronic: thin barrier layer metal on a substrate layer, and a conductive material encapsulated by the thin barrier layer; capacitors; computer systems
05/20/2003US6566699 Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
05/20/2003US6566698 Ferroelectric-type nonvolatile semiconductor memory and operation method thereof
05/20/2003US6566696 Self-aligned VT implant
05/20/2003US6566693 Reduced capacitance scaled HBT using a separate base post layer
05/20/2003US6566691 Semiconductor device with trench gate having structure to promote conductivity modulation
05/20/2003US6566690 Single feature size MOS technology power device
05/20/2003US6566687 Metal induced self-aligned crystallization of Si layer for TFT
05/20/2003US6566686 Thin-film transistor display devices
05/20/2003US6566684 Active matrix circuit having a TFT with pixel electrode as auxiliary capacitor
05/20/2003US6566683 Laser heat treatment method, laser heat treatment apparatus, and semiconductor device
05/20/2003US6566682 Programmable memory address and decode circuits with ultra thin vertical body transistors
05/20/2003US6566680 Semiconductor-on-insulator (SOI) tunneling junction transistor
05/20/2003US6566678 Semiconductor device having a solid-state image sensor
05/20/2003US6566677 Nitride-based semiconductor device and manufacturing method thereof
05/20/2003US6566671 Microscopic defect inspection apparatus and method thereof, as well as positional shift calculation circuit therefor
05/20/2003US6566667 Plasma focus light source with improved pulse power system
05/20/2003US6566666 Method and apparatus for pyroelectric lithography using patterned emitter
05/20/2003US6566662 Charged beam exposure system
05/20/2003US6566661 Ion implanter with wafer angle and faraday alignment checking
05/20/2003US6566654 Detecting secondary electrons emitted as a result of irradiation of the circuit pattern with the electron beam, forming images of the irradiated first and second regions, extracting a difference between the formed images
05/20/2003US6566632 Hot plate and semiconductor device manufacturing method using the same
05/20/2003US6566630 Thermal processing apparatus for introducing gas between a target object and a cooling unit for cooling the target object
05/20/2003US6566612 Method for direct chip attach by solder bumps and an underfill layer
05/20/2003US6566595 Solar cell and process of manufacturing the same
05/20/2003US6566422 For bonding and connecting elements each having electrodes thereon
05/20/2003US6566315 Also containing an orgamic amine and a nitrogen-containing carboxylic acid or imine
05/20/2003US6566284 Method of manufacture for 80 nanometer diameter resonant tunneling diode with improved peak-to-valley ratio and resonant tunneling diode therefrom
05/20/2003US6566283 Silane treatment of low dielectric constant materials in semiconductor device manufacturing
05/20/2003US6566282 Method of forming a silicon oxide layer
05/20/2003US6566281 Nitrogen-rich barrier layer and structures formed
05/20/2003US6566280 Forming polymer features on a substrate
05/20/2003US6566279 Method for fabricating a SiC film and a method for fabricating a SiC multi-layered film structure
05/20/2003US6566278 Method for densification of CVD carbon-doped silicon oxide films through UV irradiation
05/20/2003US6566277 Liquid-phase growth method, liquid-phase growth apparatus, and solar cell
05/20/2003US6566276 Method of making electronic materials
05/20/2003US6566275 Spinner apparatus with chemical supply nozzle and methods of forming patterns and performing etching using the same
05/20/2003US6566273 Etch selectivity inversion for etching along crystallographic directions in silicon
05/20/2003US6566272 Method for providing pulsed plasma during a portion of a semiconductor wafer process
05/20/2003US6566271 Method of producing a semiconductor surface covered with fluorine
05/20/2003US6566270 Integration of silicon etch and chamber cleaning processes
05/20/2003US6566269 Removal of post etch residuals on wafer surface
05/20/2003US6566268 Method and apparatus for planarizing a wafer surface of a semiconductor wafer having an elevated portion extending therefrom
05/20/2003US6566267 Inexpensive process for producing a multiplicity of semiconductor wafers
05/20/2003US6566266 Method of polishing a layer comprising copper using an oxide inhibitor slurry
05/20/2003US6566264 Method for forming an opening in a semiconductor device substrate
05/20/2003US6566263 Method of forming an HDP CVD oxide layer over a metal line structure for high aspect ratio design rule
05/20/2003US6566262 Method for creating self-aligned alloy capping layers for copper interconnect structures
05/20/2003US6566261 Semiconductor device and method of manufacturing the same
05/20/2003US6566260 Non-metallic barrier formations for copper damascene type interconnects
05/20/2003US6566259 Integrated deposition process for copper metallization
1 ... 4682 4683 4684 4685 4686 4687 4688 4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 ... 6590