| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 05/22/2003 | WO2003042072A1 A bag |
| 05/22/2003 | WO2003042071A1 Wafer carrier with wafer retaining system |
| 05/22/2003 | WO2003042059A1 Wafer enclosure sealing arrangement for wafer containers |
| 05/22/2003 | WO2003041937A1 Composite kinematic coupling |
| 05/22/2003 | WO2003041880A1 Semiconductor wafer cleaning systems and methods |
| 05/22/2003 | WO2003041845A1 Decomposing agent and method of decomposition treatment for sulfur fluorides |
| 05/22/2003 | WO2003024186A3 Methods and apparatus for patterning a surface |
| 05/22/2003 | WO2003019651A3 Through-via vertical interconnects, through-via heat sinks and associated fabrication methods |
| 05/22/2003 | WO2003019564A3 Magnetoresistive level generator |
| 05/22/2003 | WO2003012951A3 Esd protection devices for a differential pair of transistors |
| 05/22/2003 | WO2003009340A3 Device and method for harmonised positioning of wafer disks |
| 05/22/2003 | WO2003007396A3 Lamellar polymer architecture |
| 05/22/2003 | WO2003003457A3 Design of lithography alignment and overlay measurement marks on damascene surface |
| 05/22/2003 | WO2002099839A3 Wafer bias drive for a plasma source |
| 05/22/2003 | WO2002099165A3 Tools with transfer devices for handling workpieces |
| 05/22/2003 | WO2002090922A3 Method and apparatus for nondestructive measurement and mapping of sheet materials |
| 05/22/2003 | WO2002082532A3 Semiconductor test system and associated methods for wafer level acceptance testing |
| 05/22/2003 | WO2002073657A3 Semiconductor memory location comprising a trench capacitor and method for the production thereof |
| 05/22/2003 | WO2002065507A3 Dynamic memory based on single electron storage |
| 05/22/2003 | WO2002063404A3 Multi-channel temperature control system for semiconductor processing facilities |
| 05/22/2003 | WO2002059968B1 Integrated circuits protected against reverse engineering using an apparent metal contact line terminating on field oxide and method |
| 05/22/2003 | WO2002058109A3 Reduced aspect ratio digit line contact process flow used during the formation of a semiconductor dram device |
| 05/22/2003 | WO2002056912A3 Pharmaceutical combination for the treatment of cancer containing a 4-quinazolineamine and another anti-neoplastic agent |
| 05/22/2003 | WO2002047159A3 Dram with vertical transistor and trench capacitor memory cells and method of fabrication |
| 05/22/2003 | WO2002031859A9 Stepped upper electrode for plasma processing uniformity |
| 05/22/2003 | WO2002029889A3 Vertical transistor dram cell and method of making the same |
| 05/22/2003 | WO2001000137A3 Apparatus and method for setting the parameters of an alert window used for timing the delivery of etc signals to a heart under varying cardiac conditions |
| 05/22/2003 | US20030097647 Method and apparatus for mixed-mode optical proximity correction |
| 05/22/2003 | US20030097641 Method of designing semiconductor device and semiconductor device |
| 05/22/2003 | US20030097609 Flash EEprom system |
| 05/22/2003 | US20030097198 Method and apparatus for utilizing integrated metrology data as feed-forward data |
| 05/22/2003 | US20030097008 Chemical amplified resist, polymer for the chemically amplified resist, monomer for the polymer and method for transferring pattern to chemically amplified resist layer |
| 05/22/2003 | US20030096938 Incorporating thermosetting monomer has a cage compound or aryl core structure, plurality of arms that are covalently bound to the cage compound or core structure into a polymer to form the low dielectric constant polymer |
| 05/22/2003 | US20030096903 Method for reducing pattern dimension in photoresist layer |
| 05/22/2003 | US20030096564 Wafer polishing apparatus |
| 05/22/2003 | US20030096523 Contactor for semiconductor device and contact method |
| 05/22/2003 | US20030096519 Microspring with conductive coating deposited on tip after release |
| 05/22/2003 | US20030096508 Reactive sputtering a metal oxide layer from a target of the metal onto the substrate characterised in that the support is biased to induce a direct current (DC) voltage across the depositing dielectric as it forms; making capacitors |
| 05/22/2003 | US20030096507 Backside protection films |
| 05/22/2003 | US20030096506 Method of controlling striations and CD loss in contact oxide etch |
| 05/22/2003 | US20030096505 Manufacturing method of semiconductor device |
| 05/22/2003 | US20030096504 Improving an etch selectivity of an etch target against a photoresist pattern using difluoromethane (CH2F2) and perfluorocyclobutane (C4F6) mixed gas |
| 05/22/2003 | US20030096503 Method of fabricating a semiconductor device |
| 05/22/2003 | US20030096501 For MIS (metal insulator semiconductor) transistor of which gate length, the width of the gate electrode is less than 0.1 mu m; gate insulating film is made of a high dielectric constant material |
| 05/22/2003 | US20030096500 Process for removing contaminant from a surface and composition useful therefor |
| 05/22/2003 | US20030096499 Method for integrated nucleation and bulk film deposition |
| 05/22/2003 | US20030096498 For preparing semiconductors for a plating process; chemical mechanical polishing |
| 05/22/2003 | US20030096497 Electrode structure for use in an integrated circuit |
| 05/22/2003 | US20030096496 Method of forming dual damascene structure |
| 05/22/2003 | US20030096495 Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device |
| 05/22/2003 | US20030096494 Method of making semiconductor device |
| 05/22/2003 | US20030096492 Comprises dielectric film on wafer and forms mask pattern containing functional element or wire; miniaturization |
| 05/22/2003 | US20030096491 Method for fabricating a semiconductor device having a metallic silicide layer |
| 05/22/2003 | US20030096490 Amorphizing semiconductor material with silicon to particluar depth, doping, then annealing at temperature consistent with solid phase epitaxy regrowth, activating the junction |
| 05/22/2003 | US20030096489 Processing amorphous silicon with excimer laser pulsation, and translating positioning of sample with respect to slit patterned beamlets |
| 05/22/2003 | US20030096488 Method and semiconductor wafer configuration for producing an alignment mark for semiconductor wafers |
| 05/22/2003 | US20030096487 Method of forming an integrated inductor and high speed interconnect in a planarized process with shallow trench isolation |
| 05/22/2003 | US20030096486 Reduced photolithographic processing; semiconductors |
| 05/22/2003 | US20030096485 Fabricating a DMOS transistor |
| 05/22/2003 | US20030096484 Method of fabricating MOS transistor having shallow source/drain junction regions |
| 05/22/2003 | US20030096483 Method of manufacturing mos transistor with fluoride implantation on silicon nitride etching stop layer |
| 05/22/2003 | US20030096482 Dense trench MOSFET with decreased etch sensitivity to deposition and etch processing |
| 05/22/2003 | US20030096481 Metal-oxide field effect transistor (MOSFET) comprising dielectric layer and implanted electroconductive dopants |
| 05/22/2003 | US20030096480 Method for forming trench MOSFET device with low parasitic resistance |
| 05/22/2003 | US20030096479 Method of forming narrow trenches in semiconductor substrates |
| 05/22/2003 | US20030096478 Lateral bipolar transistor and method for producing the same |
| 05/22/2003 | US20030096477 Process for manufacturing a non-volatile memory cell with a floating gate region autoaligned to the isolation and with a high coupling coefficient |
| 05/22/2003 | US20030096476 Protective layer in memory device and method therefor |
| 05/22/2003 | US20030096475 Protective layer in memory device and method therefor |
| 05/22/2003 | US20030096474 Capacitor of semiconductor device and fabrication method thereof |
| 05/22/2003 | US20030096473 Having high-k dielectrics with high unit capacitance, reduced leakage current, increased breakdown voltages and reduced capacitor dependence on applied voltage; forming a a high-k dielectric film sandwiched between two wide-band-gap oxide |
| 05/22/2003 | US20030096472 Oxygen radical annealing or plasma annealing a lower or upper electrode or a dielectric layer of a microelectronic capacitor on a substrate to reduce the leakage current and the impurities in the dielectric layer |
| 05/22/2003 | US20030096471 Formation of dual work function gate electrode |
| 05/22/2003 | US20030096470 Resolving etching defects to give predetermined properties and stability by removing a surface oxidized layer formed on the emitter layer; forming a region in which a collector electrode is disposed for wet etching other layers |
| 05/22/2003 | US20030096469 Lifting during cleaning is prevented by improving adhesive strength between an upper electrode and an interlayer dielectric layer in a capacitor formed on a semiconductor substrate; a high-speed, rewritable nonvolatile memory cell |
| 05/22/2003 | US20030096468 Method of growing electrical conductors |
| 05/22/2003 | US20030096467 Semiconductors having a high K dielectric as a hafnium oxide gate with excellent leakage current and low interface state with a gate electrode and silicon substrate; a gate dielectric on a trench ; a gate line on the gate dielectric |
| 05/22/2003 | US20030096466 A substrate having a low voltage and a high voltage section; forming a first and second layer as a thick gate dielectric layer; removing the thick gate dielectric layer from the low voltage section to form a thin gate dielectric layer there |
| 05/22/2003 | US20030096465 Hard mask trimming with thin hard mask layer and top protection layer |
| 05/22/2003 | US20030096464 Method for forming a schottky diode on a silicon carbide substrate |
| 05/22/2003 | US20030096463 Reduces an element area greatly by reducing source/drain areas of a transistor; increases on-current by extensively reducing distances between a gate electrode and source/drain electrodes (wiring lines); power saving; high definition |
| 05/22/2003 | US20030096462 Suppress deterioration of the transistor caused by ion channeling by controlling the silicon layer so the gate insulating film side of the silicon is an amorphous layer and the surface side of is a crystalline layer; durability |
| 05/22/2003 | US20030096461 Integrated circuit resistant to the formation of cracks in a passivation layer |
| 05/22/2003 | US20030096460 Each pixel has an n-channel type thin film transistor; a channel forming region in contact with a first doped region; a second doped region of different conductivity overlapping the first; prevent increase of OFF current and decrease of ON |
| 05/22/2003 | US20030096459 Crystalline silicon thin film transistor panel for LCD and method of fabricating the same |
| 05/22/2003 | US20030096458 Method of manufacturing thin film transistor |
| 05/22/2003 | US20030096457 Sonic transducers bonded with polymers and methods of making same for efficient sonic energy transfer |
| 05/22/2003 | US20030096456 Semiconductor devices having their exposed edges defined by cutting apart two of the semiconductor preassembly; then moving the first semiconductor device against another element to break loose flash on the first exposed edge; appearance |
| 05/22/2003 | US20030096455 Method of manufacturing semiconductor device having tie bars for interconnecting leads |
| 05/22/2003 | US20030096453 Integrated void-free process for assembling a solder bumped chip |
| 05/22/2003 | US20030096452 Method of applying no-flow underfill |
| 05/22/2003 | US20030096451 Good electroconductivity between an integrated circuit chip and a circuit substrate by a dicing step for dividing a semiconductor wafer, washing, bump-bonding while the wafer is being attached to the carrier, and mounting |
| 05/22/2003 | US20030096449 Chip scale package provided with a stress relieving layer having a sloping edge and specific size wiring over it from the electrodes; allows the ommission of a patterned flexible substrate and many components to be made simultaneously |
| 05/22/2003 | US20030096448 Selective solder bump application |
| 05/22/2003 | US20030096446 Electrode patterning in OLED devices |
| 05/22/2003 | US20030096445 Manufacturing method for two-dimensional image detectors and two-dimensional image detectors |
| 05/22/2003 | US20030096444 Having epitaxially grown semiconductor layers; reduced crystal defects |
| 05/22/2003 | US20030096442 Forming photodiode in semiconductor substrate, forming transfer, reset, drive, and select transistors, forming insulating layer containing hydrogen ions, forming second insulating layer, diffusing hydrogen into photodiode |
| 05/22/2003 | US20030096441 Reduces number of steps in etching process using masks; invention relates to photosensitive cell array for detection of non-visible light ray such as an X-ray |
| 05/22/2003 | US20030096440 Method for forming a semiconductor device for detecting light |