Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2003
11/11/2003US6646349 Ball grid array semiconductor package
11/11/2003US6646348 Silane containing polishing composition for CMP
11/11/2003US6646347 Semiconductor power device and method of formation
11/11/2003US6646346 Integrated circuit metallization using a titanium/aluminum alloy
11/11/2003US6646345 Method for forming Co-W-P-Au films
11/11/2003US6646342 Semiconductor chip and multi-chip module
11/11/2003US6646339 Thin and heat radiant semiconductor package and method for manufacturing
11/11/2003US6646332 Semiconductor package device
11/11/2003US6646331 Semiconductor device and semiconductor module
11/11/2003US6646330 Lead frame for semiconductor device, process for producing the same and semiconductor device using the same
11/11/2003US6646327 Semiconductor device and semiconductor device manufacturing method
11/11/2003US6646326 Method and system for providing source/drain-gate spatial overlap engineering for low-power devices
11/11/2003US6646325 Semiconductor device having a step-like section on the back side of the substrate, and method for manufacturing the same
11/11/2003US6646324 Method and apparatus for a linearized output driver and terminator
11/11/2003US6646323 Zero mask high density metal/insulator/metal capacitor
11/11/2003US6646322 Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
11/11/2003US6646320 Method of forming contact to poly-filled trench isolation region
11/11/2003US6646319 Semiconductor device having isolating region for suppressing electrical noise
11/11/2003US6646313 Semiconductor integrated circuit device and having deposited layer for gate insulation
11/11/2003US6646312 Semiconductor memory device with bit lines having reduced cross-talk
11/11/2003US6646311 Vertical bipolar transistor formed using CMOS processes
11/11/2003US6646308 Flat panel display device
11/11/2003US6646307 MOSFET having a double gate
11/11/2003US6646306 Semiconductor device
11/11/2003US6646304 Universal semiconductor wafer for high-voltage semiconductor components
11/11/2003US6646303 Nonvolatile semiconductor memory device and a method of manufacturing the same
11/11/2003US6646302 Embedded metal nanocrystals
11/11/2003US6646301 Floating gate semiconductor device
11/11/2003US6646300 Semiconductor memory device
11/11/2003US6646299 Integrated circuit configuration having at least two capacitors and method for manufacturing an integrated circuit configuration
11/11/2003US6646298 Capacitor with oxygenated metal electrodes and high dielectric constant materials
11/11/2003US6646296 Semiconductor integrated circuit and method for manufacturing the same
11/11/2003US6646295 Semiconductor device
11/11/2003US6646293 Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates
11/11/2003US6646288 Current control p-channel thin film transistor resistant to hot carrier injection; reliability; efficiency
11/11/2003US6646287 Semiconductor device with tapered gate and insulating film
11/11/2003US6646281 Differential detector coupled with defocus for improved phase defect sensitivity
11/11/2003US6646274 Lithographic projection apparatus
11/11/2003US6646243 Fixing biopolymers to substrate; obtain substrate, incubate with nucleotide sequences, expose to activator, recover product
11/11/2003US6646236 Hot plate unit
11/11/2003US6646235 High temperature uniformity; chemical resistance
11/11/2003US6646233 Wafer stage for wafer processing apparatus and wafer processing method
11/11/2003US6646223 Method for improving ash rate uniformity in photoresist ashing process equipment
11/11/2003US6646063 Semiconductor device and process for producing the same, and tablet comprising epoxy resin composition
11/11/2003US6645885 Forming indium nitride (InN) and indium gallium nitride (InGaN) quantum dots grown by metal-organic-vapor-phase-epitaxy (MOCVD)
11/11/2003US6645884 Method of forming a silicon nitride layer on a substrate
11/11/2003US6645883 Vapor deposition using diluent gas
11/11/2003US6645882 Preparation of composite high-K/standard-K dielectrics for semiconductor devices
11/11/2003US6645881 Method of forming coating film, method of manufacturing semiconductor device and coating solution
11/11/2003US6645880 Treating solution applying method
11/11/2003US6645879 Method of forming a silicon oxide layer of a semiconductor device and method of forming a wiring having the same
11/11/2003US6645878 Low volatility solvent-based method for forming thin film nanoporous aerogels on semiconductor substrates
11/11/2003US6645877 Method of operating a processing chamber having multiple stations
11/11/2003US6645876 Etching for manufacture of semiconductor devices
11/11/2003US6645875 Method of processing metal and method of manufacturing semiconductor device using the metal
11/11/2003US6645874 Delivery of dissolved ozone
11/11/2003US6645873 Etching silicon oxide doped with fluorine with hydrogen fluoride; forming hollow structures in semiconductor
11/11/2003US6645872 Chemically enhanced focused ion beam micro-machining of copper
11/11/2003US6645871 Method of holding substrate and substrate holding system
11/11/2003US6645870 Process for fabricating semiconductor device
11/11/2003US6645869 Etching back process to improve topographic planarization of a polysilicon layer
11/11/2003US6645868 Method of forming shallow trench isolation using antireflection layer
11/11/2003US6645867 Structure and method to preserve STI during etching
11/11/2003US6645866 Method of fabricating a semiconductor device using trench isolation method including hydrogen annealing step
11/11/2003US6645865 Methods, apparatuses and substrate assembly structures for fabricating microelectronic components using mechanical and chemical-mechanical planarization processes
11/11/2003US6645864 Physical vapor deposition of an amorphous silicon liner to eliminate resist poisoning
11/11/2003US6645863 Method of manufacturing semiconductor device and semiconductor device
11/11/2003US6645862 Double-side polishing process with reduced scratch rate and device for carrying out the process
11/11/2003US6645861 Process control; overcoating silicone with metal; anisotropic etching; rapid thermal annealing
11/11/2003US6645860 Adhesion promotion method for CVD copper metallization in IC applications
11/11/2003US6645859 Semiconductor device and manufacturing method thereof
11/11/2003US6645858 Method of catalyzing copper deposition in a damascene structure by plasma treating the barrier layer and then applying a catalyst such as iodine or iodine compounds to the barrier layer
11/11/2003US6645857 Key hole filling
11/11/2003US6645856 Method for manufacturing a semiconductor device using half-tone phase-shift mask to transfer a pattern onto a substrate
11/11/2003US6645854 Formation of a vertical junction throuph process simulation based optimization of implant doses and energies
11/11/2003US6645853 Interconnects with improved barrier layer adhesion
11/11/2003US6645852 Process for fabricating a semiconductor device having recess portion
11/11/2003US6645851 Method of forming planarized coatings on contact hole patterns of various duty ratios
11/11/2003US6645850 Semiconductor device having cavities with submicrometer dimensions generated by a swelling process
11/11/2003US6645849 Method for manufacturing semiconductor device for suppressing detachment of conductive layer
11/11/2003US6645848 Method of improving the fabrication of etched semiconductor devices
11/11/2003US6645847 Microelectronic interconnect material with adhesion promotion layer and fabrication method
11/11/2003US6645846 Laminating with insulative material, anisotropically etching to form a sidewall etch stop, selectively etching a contact opening through the laminated layer
11/11/2003US6645845 Methods of forming interconnect regions of integrated circuitry
11/11/2003US6645842 Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
11/11/2003US6645841 In a solder bump integrated circuit packaging process so that portions of a circuit can be effectively disabled
11/11/2003US6645840 Forming two layers, etching the top one and oxidizing to form a notch, where the bottom layer oxidizes at a faster rate than the top layer; making a transistor gate
11/11/2003US6645839 Method for improving a doping profile for gas phase doping
11/11/2003US6645838 Selective absorption process for forming an activated doped region in a semiconductor
11/11/2003US6645837 Method of manufacturing semiconductor device
11/11/2003US6645836 Method of forming a semiconductor wafer having a crystalline layer thereon containing silicon, germanium and carbon
11/11/2003US6645835 Semiconductor film forming method and manufacturing method for semiconductor devices thereof
11/11/2003US6645834 Method for manufacturing annealed wafer and annealed wafer
11/11/2003US6645833 Method for producing layered structures on a substrate, substrate and semiconductor components produced according to said method
11/11/2003US6645832 Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack
11/11/2003US6645831 Thermally stable crystalline defect-free germanium bonded to silicon and silicon dioxide
11/11/2003US6645830 Separation layer is irradiated with incident light so as to cause exfoliation in separation layer and/or at the interface, and to detach detached member from substrate
11/11/2003US6645829 Optoelectronic integrated circuit (OEIC); outermost epitaxial layer exposed to the chemical-mechanical processing equipment is always silicon or silicon dioxide
11/11/2003US6645828 In situ plasma wafer bonding method
11/11/2003US6645827 Method for forming isolation regions on semiconductor device
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