Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2003
11/06/2003US20030207490 Wafer level underfill and interconnect process
11/06/2003US20030207488 Flexible organic electronic device with improved resistance to oxygen and moisture degradation
11/06/2003US20030207486 Low remanence flux concentrator for MRAM devices
11/06/2003US20030207480 Method of manufacturing semiconductor device
11/06/2003US20030207477 Devices and methods for integrated circuit manufacturing
11/06/2003US20030207476 Apparatus and method for optical evaluation, apparatus and method for manufacturing semiconductor device, method of controlling apparatus for manufacturing semiconductor device, and semiconductor device
11/06/2003US20030207474 Method for semiconductor yield loss calculation
11/06/2003US20030207473 Method of forming ferroelectric thin films on a high-k layer
11/06/2003US20030207472 Method for controlling deposition of dielectric films
11/06/2003US20030207471 Self-aligned, trenchless mangetoresitive random-access memory (MRAM) structure with sidewall containment of MRAM structure
11/06/2003US20030207470 Metal insulator semiconductor structure with polarization-compatible buffer layer
11/06/2003US20030207214 Mass production method of semiconductor integrated curcuit device and manufacturing method of electronic device
11/06/2003US20030207208 Intermediate layer composition for three-layer resist process and pattern formation method using the same
11/06/2003US20030207207 Structure employs a dual hardmask technique in a dual damascene process. The method includes using amorphous carbon as a first hardmask layer capable of being etched by a second etch process, and a second hardmask layer capable of being
11/06/2003US20030207205 Provides photoresist monomers, photoresist polymers derived from the same, processes for producing such photoresist polymers, photoresist compositions comprising such polymers, and processes for producing a photoresist pattern using such
11/06/2003US20030207183 Manufacturing method of a phase-shift mask, method of forming a resist pattern and manufacturing method of a semiconductor device
11/06/2003US20030207181 Mask includes a mask substrate and mask patterns arranged on the mask substrate such that a critical dimension (CD), represented by the width of each of the mask patterns, and a phase of the mask patterns have a size proportional to a SINC
11/06/2003US20030207180 Dual damascene process using a single photo mask
11/06/2003US20030207150 Methods of controlling oxygen partial pressure during annealing of a perovskite dielectric layer
11/06/2003US20030207147 Enhancement, stabilization and metallization of porous silicon
11/06/2003US20030207132 The present invention relates to oxides on suitable substrates, as converted from nitride precursors. Oxidation of compounds for fabrication of a ferro-electric device.
11/06/2003US20030207131 Low dielectric constant film material, film and semiconductor device using such material
11/06/2003US20030207127 Method of forming a germanium film on a semiconductor substrate that includes the formation of a graded silicon-germanium buffer layer prior to the formation of a germanium layer
11/06/2003US20030207125 Base substrate for crystal growth and manufacturing method of substrate by using the same
11/06/2003US20030207117 Sheet resin composition and process for manufacturing semiconductor device therewith
11/06/2003US20030207097 Multilayer structure used especially as a material of high relative permittivity
11/06/2003US20030207095 Repairing surfaces; colorimetric analysis using computer; applying primer to substrate, overcoating; measurement, calibration of color
11/06/2003US20030207093 Transparent conductive layer forming method, transparent conductive layer formed by the method, and material comprising the layer
11/06/2003US20030207044 Devices to improve the quality of the material and the device performance. The wafer or the device is coated on the back-side with a layer of aluminum and is illuminated form the other side with light having a significant portion of energy
11/06/2003US20030206838 Highly efficient compact capacitance coupled plasma reactor/generator and method
11/06/2003US20030206795 Loading and unloading station for semiconductor processing installations
11/06/2003US20030206794 Device for positioning disk-shaped objects
11/06/2003US20030206732 Heat-treating methods and systems
11/06/2003US20030206574 Temperature measuring method and apparatus in semiconductor processing apparatus, and semiconductor processing method and apparatus
11/06/2003US20030206566 Semiconductor laser device and fabricating method thereof
11/06/2003US20030206473 Method and system for performing equipotential sensing across a memory array to eliminate leakage currents
11/06/2003US20030206472 Semiconductor memory device including an SOI substrate
11/06/2003US20030206465 Integrated memory with a configuration of non-volatile memory cells and method for fabricating and for operating the integrated memory
11/06/2003US20030206463 Low-power consumption semiconductor memory device
11/06/2003US20030206461 Magnetoresistive memory (MRAM)
11/06/2003US20030206459 Semiconductor device array having dense memory cell array and hierarchical bit line scheme
11/06/2003US20030206447 Nonvolatile memory structures and fabrication methods
11/06/2003US20030206443 Nonvolatile semiconductor memory and method of manufacturing the same
11/06/2003US20030206440 Bi-directional floating gate nonvolatile memory
11/06/2003US20030206439 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield
11/06/2003US20030206437 Floating-gate semiconductor structures
11/06/2003US20030206434 Layout for thermally selected cross-point mram cell
11/06/2003US20030206432 Minimizing errors in a magnetoresistive solid-state storage device
11/06/2003US20030206430 Ferroelectric memory
11/06/2003US20030206426 Inverter controller
11/06/2003US20030206389 Highly efficient capacitor structures with enhanced matching properties
11/06/2003US20030206337 Exposure apparatus for irradiating a sensitized substrate
11/06/2003US20030206303 Overlay alignment mark design
11/06/2003US20030206295 Sample inspection system
11/06/2003US20030206289 Imaging optical system evaluation method, imaging optical system adjustment method, exposure apparatus and exposure method
11/06/2003US20030206283 Method of manufacturing a device by employing a lithographic apparatus including a sliding electron-optical element
11/06/2003US20030206049 Semiconductor integrated circuit
11/06/2003US20030206047 Power integrated circuit with distributed gate driver
11/06/2003US20030206035 Conductive material for integrated circuit fabrication
11/06/2003US20030206034 Method of temporarily securing a die to a burn-in carrier
11/06/2003US20030206030 Universal wafer carrier for wafer level die burn-in
11/06/2003US20030206010 Method for monitoring a metal layer during chemical mechanical polishing using a phase difference signal
11/06/2003US20030205997 Wafer probe station having environment control enclosure
11/06/2003US20030205993 Voltage generating circuit and reference voltage source circuit employing field effect transistors
11/06/2003US20030205969 Organic electroluminescent display device and method of fabricating the same
11/06/2003US20030205905 Wafer holder
11/06/2003US20030205845 Planarization layers cover only the active areas; and barrier layers cover only said planarization layers.
11/06/2003US20030205837 Device comprising components vertically stacked thereon and method for manufacturing the same
11/06/2003US20030205829 Rad Hard MOSFET with graded body diode junction and reduced on resistance
11/06/2003US20030205828 Transfer mold packaging with conductive traces; soldermask has a openings to locations on the conductive traces and includes a elongated trench to align with an elongated mold void perimeter of a transfer mold
11/06/2003US20030205827 Wirebond structure and method to connect to a microelectronic die
11/06/2003US20030205825 Structure for connecting interconnect lines and method of manufacturing same
11/06/2003US20030205824 Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack
11/06/2003US20030205823 Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics
11/06/2003US20030205822 Low-strength plasma treatment for interconnects
11/06/2003US20030205820 Semiconductor device and method of manufacturing the same
11/06/2003US20030205819 Physically deposited layer to electrically connect circuit edit connection targets
11/06/2003US20030205818 Semiconductor device and method for manufacturing the same
11/06/2003US20030205817 Process for making low dielectric constant hollow chip structures by removing sacrificial dielectric material after the chip is joined to a carrier
11/06/2003US20030205816 Integrated circuit configuration with analysis protection and method for producing the configuration
11/06/2003US20030205815 Fabrication method of integrated circuits with borderless vias and low dielectric constant inter-metal dielectrics
11/06/2003US20030205814 Wiring structure of semiconductor device
11/06/2003US20030205813 Method of forming a multi-layered wiring structure incorporation in semiconductor intergrated circuit device and having large electromigration resistance.
11/06/2003US20030205812 Semiconductor device protective overcoat with enhanced adhesion to polymeric materials and method of fabrication
11/06/2003US20030205811 Method for fabricating semiconductor integrated circuit
11/06/2003US20030205810 Semiconductor device and manufacturing method thereof
11/06/2003US20030205809 Barrier material encapsulation of programmable material
11/06/2003US20030205805 Partial slot cover for encapsulation process
11/06/2003US20030205799 Method and device for assembly of ball grid array packages
11/06/2003US20030205798 Semiconductor die package including carrier with mask
11/06/2003US20030205797 Method of manufacturing a semiconductor device and a semiconductor device
11/06/2003US20030205796 Method of forming an integrated semiconductor device having co-planar device surfaces
11/06/2003US20030205794 Flip-chip bonding structure and method for making the same
11/06/2003US20030205793 Wire-bonded chip on board package
11/06/2003US20030205792 Semiconductor device packaging assembly and method for manufacturing the same
11/06/2003US20030205787 Semiconductor device having a fuse
11/06/2003US20030205785 Low k film application for interlevel dielectric and method of cleaning etched features
11/06/2003US20030205784 Capable of preventing bubble defects.
11/06/2003US20030205782 Passivation integrity improvements
11/06/2003US20030205781 Method of manufacturing a device with epitaxial base
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