Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2003
11/06/2003US20030207777 Cleaning compositions
11/06/2003US20030207750 Forming a low k fluorine and carbon- containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes including one or more organofluoro silanes characterized by the absence of aliphatic C-H bonds
11/06/2003US20030207664 Device for integrating a vacuum pumping system in a clean room false floor of a semiconductor component manufacturing plant
11/06/2003US20030207655 Dense fluid spray cleaning process and apparatus
11/06/2003US20030207654 Polishing device and polishing method for semiconductor wafer
11/06/2003US20030207651 Polishing endpoint detecting method, device for detecting a polishing endpoint of a polishing process and chemical-mechanical polishing apparatus comprising the same
11/06/2003US20030207596 Platen for electrostatic wafer clamping apparatus
11/06/2003US20030207595 Semiconductor device having a low dielectric constant dielectric material and process for its manufacture
11/06/2003US20030207594 Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for intergrated circuit structure
11/06/2003US20030207593 Atomic layer deposition and conversion
11/06/2003US20030207592 Method of forming a capacitor dielectric layer
11/06/2003US20030207591 A method for high temperature oxide layer anneal to prevent oxide edge peeling
11/06/2003US20030207590 Lower temperature method for forming high quality silicon-nitrogen dielectrics
11/06/2003US20030207589 Method for growing a monocrystalline oxide layer and for fabricating a semiconductor device on a monocrystalline substrate
11/06/2003US20030207588 Semiconductor configuration and process for etching a layer of the semiconductor configuration using a silicon-containing etching mask
11/06/2003US20030207587 Semiconductor constructions; and methods of forming semiconductor constructions
11/06/2003US20030207586 Dual layer etch stop barrier
11/06/2003US20030207585 Method of etching silicon nitride spacers with high selectivity relative to oxide in a high density plasma chamber
11/06/2003US20030207584 Patterning tighter and looser pitch geometries
11/06/2003US20030207583 Method for processing wafer using single frequency RF power in plasma processing chamber
11/06/2003US20030207581 Plasma etching methods
11/06/2003US20030207580 HDP-CVD dep/etch/dep process for improved deposition into high aspect ratio features
11/06/2003US20030207579 Method of etching a deep trench having a tapered profile in silicon
11/06/2003US20030207578 Method and apparatus for controlling material removal from a semiconductor substrate using induced current endpointing
11/06/2003US20030207577 Polishing polymer surfaces on nonporous CMP pads
11/06/2003US20030207576 Method and device for inspecting surface of semiconductor device
11/06/2003US20030207575 Device isolation process flow for ARS system
11/06/2003US20030207574 Semiconductor device manufacturing method having a step of applying a copper foil on a substrate as a part of a wiring connecting an electrode pad to a mounting terminal
11/06/2003US20030207573 Charge separation type heterojunction structure and manufacturing method therefor
11/06/2003US20030207571 Gate technology for strained surface channel and strained buried channel MOSFET devices
11/06/2003US20030207569 Process for forming a low resistivity titanium silicide layer on a silicon semiconductor substrate and the resulting device
11/06/2003US20030207567 Metal film pattern and manufacturing method thereof
11/06/2003US20030207566 High performance silicon contact for flip chip
11/06/2003US20030207565 Novel technique to achieve thick silicide film for ultra-shallow junctions
11/06/2003US20030207564 Copper dual damascene interconnect technology
11/06/2003US20030207563 Method for photoresist strip, sidewall polymer removal and passivation for aluminum metallization
11/06/2003US20030207562 Method and apparatus for improving adhesion between layers in integrated devices
11/06/2003US20030207561 Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs
11/06/2003US20030207560 Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures
11/06/2003US20030207559 Method for eliminating VIA resistance shift in organic ILD
11/06/2003US20030207558 Method forming copper containing semiconductor features to prevent thermally induced defects
11/06/2003US20030207557 Semiconductor device and its manufacturing method
11/06/2003US20030207556 Forming a conductive structure in a semiconductor device
11/06/2003US20030207555 Semiconductor device and method of fabricating the same
11/06/2003US20030207554 Method for making semiconductor device
11/06/2003US20030207553 Method for fabricating semiconductor device and forming interlayer dielectric film using high-density plasma
11/06/2003US20030207552 Raw material compounds for use in cvd, and chemical vapor deposition for producing iridium or iridium compound thin films
11/06/2003US20030207551 Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates, and gallium nitride semiconductor structures fabricated thereby
11/06/2003US20030207550 Ultra thin tungsten metal films used as adhesion promoter between barrier metals and copper
11/06/2003US20030207549 Method of forming a silicate dielectric layer
11/06/2003US20030207548 Semiconductor device and method of manufacturing the same
11/06/2003US20030207547 Silicon deposition process in resistively heated single wafer chamber
11/06/2003US20030207546 Mother substrate, substrate element, and method for manufacturing the same
11/06/2003US20030207545 SOI substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the SOI substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus
11/06/2003US20030207544 Semiconductor device and process of producing the same
11/06/2003US20030207543 Structure and method of MOS transistor having increased substrate resistance
11/06/2003US20030207542 Fabrication of abrupt ultra-shallow junctions using angled pai and fluorine implant
11/06/2003US20030207541 Method for protecting MOS components from antenna effect and the apparatus thereof
11/06/2003US20030207540 Atomic layer-deposited laaio3 films for gate dielectrics
11/06/2003US20030207539 Low thermal budget fabrication method for a mask read only memory device
11/06/2003US20030207538 Trench DMOS transistor with embedded trench schottky rectifier
11/06/2003US20030207536 Semiconductor device with alternating conductivity type layer and method of manufacturing the same
11/06/2003US20030207535 Semiconductor device and method for fabricating the same
11/06/2003US20030207534 System for fabricating a metal/anti-reflective coating/insulator/metal (maim) capacitor
11/06/2003US20030207533 Forming electronic structures having dual dielectric thicknesses and the structure so formed
11/06/2003US20030207532 Method and structure for salicide trench capacitor plate electrode
11/06/2003US20030207531 Method for forming polysilicon connected deep trench dram cell
11/06/2003US20030207530 Shallow trench isolation process for reduced junction leakage
11/06/2003US20030207529 Multi-layer film for thin film structure, capacitor using the same and fabrication method thereof
11/06/2003US20030207528 Method of making a memory cell capacitor with Ta2O5 dielectric
11/06/2003US20030207527 Flash memory array structure and method of forming
11/06/2003US20030207525 Dual depth trench isolation
11/06/2003US20030207524 Method for forming a semiconductor
11/06/2003US20030207523 Chip design with power rails under transistors
11/06/2003US20030207522 Wafer processing apparatus and wafer processing method using the same
11/06/2003US20030207521 Manufacturing use of photomasks with an opaque pattern comprising an organic layer photoabsorptive to exposure light with wavelengths exceeding 200 nm
11/06/2003US20030207520 Nonvolatile memory device with reduced floating gate and increased coupling ratio and manufacturing method thereof
11/06/2003US20030207519 Kill index analysis for automatic defect classification in semiconductor wafers
11/06/2003US20030207518 Single step pendeo- and lateral epitaxial overgrowth of Group III-nitride epitaxial layers with Group III-nitride buffer layer and resulting structures
11/06/2003US20030207517 Flash memory cell and method for fabricating a flash
11/06/2003US20030207514 Low k film application for interlevel dielectric and method of cleaning etched features
11/06/2003US20030207513 Etchant and method of etching
11/06/2003US20030207512 Self-aligned SiGe HBT on a SOI substrate
11/06/2003US20030207511 Method of fabricating a MIS transistor
11/06/2003US20030207510 Semiconductor device, and its manufacturing method, circuit substrate, and electronic apparatus
11/06/2003US20030207509 Semiconductor integrated circuit device and manufacture method therefore
11/06/2003US20030207508 Double recessed transistor
11/06/2003US20030207507 Method of manufacturing a semiconductor device and a process of a thin film transistor
11/06/2003US20030207505 Method of making transistors
11/06/2003US20030207503 Semiconductor device and method of manufacturing the same
11/06/2003US20030207502 Semiconductor device and manufacturing method therefor
11/06/2003US20030207500 Light sources comprising organic light emmiters between electrodes, used in displaying, electrophotography, recording, exposure, signs or optical communications; brightness; efficiency; durability
11/06/2003US20030207499 Compliant integrated circuit package
11/06/2003US20030207498 Partially patterned lead frames and methods of making and using the same in semiconductor packaging
11/06/2003US20030207497 Method and system for attaching semiconductor components to a substrate using local radiation curing of dicing tape
11/06/2003US20030207496 Semiconductor device and method for manufacturing the same
11/06/2003US20030207495 Stacked leads-over chip multi-chip module
11/06/2003US20030207494 Semiconductor package, semiconductor device, electronic device, and method for producing semiconductor package
11/06/2003US20030207492 Semiconductor device and method for fabricating the same
11/06/2003US20030207491 Connecting material and mounting method which uses same
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